Registered?

Discussion in 'VHDL' started by Ian, Jan 16, 2007.

  1. Ian

    Ian Guest

    Hi,

    I'm trying to simulate Error Corection Coding (Reed-Solomon)
    ip core with Xilinx Spartan FPGA as the target.
    Using ISE v8 as the interface.

    Xilinx Logicore has provided a Reed-Solomon Encoder.
    Going through the datasheet (DS251) page 2:

    "The core's synchronous input control signals
    (START, ND, BYPASS, CE) are not registered inside thecore.
    It is assumed these will be registered external to the core if
    required"

    What is the difference between a core with REGISTERED Input and
    one WITHOUT REGISTERED input?
    Does one have the advantage over the other?
    Would adding a Delay Flip-flop do?

    Thanks.
     
    Ian, Jan 16, 2007
    #1
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  2. Ian

    Joel Kolstad Guest

    "Ian" <> wrote in message
    news:...
    > "The core's synchronous input control signals
    > (START, ND, BYPASS, CE) are not registered inside thecore.
    > It is assumed these will be registered external to the core if
    > required"
    >
    > What is the difference between a core with REGISTERED Input and
    > one WITHOUT REGISTERED input?


    It means the control signals mentioned are coming out of a flip-flop that's
    clocked off the same clock that's running to the core.

    > Does one have the advantage over the other?


    Well, if you don't synchronize your control signals to the core's clock, you
    potentially end up with metastability problems (when you inadvertently
    violate the set-up and hold times of the core's internal flip-flops) and the
    core will just generate garabge data for you! Granted, for signals like
    BYPASS, CE, etc., it'll probably recover sooner or later, but the idea is
    that without synchronization there's no guarantee the thing works at all.

    The only disadvantages of the core registering the inputs itself would be
    that (1) it uses up additionally flip-flops and (2) it introduces another
    clock cycle of latency. In many cases this is a negligible difference, but
    since many people already have synchronous control signals running around
    anyway, Xilinx figures they'll go for the ever-so-slightly higher
    performance/lower gate count solution.

    > Would adding a Delay Flip-flop do?


    Just add a regular old flip-flop. Assuming the core came with a timing
    constrains file, place and route will automatically, uh... place and route
    the flip-flops such that the set-up and hold times are met on the control
    signals.

    ---Joel
     
    Joel Kolstad, Jan 16, 2007
    #2
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  3. Ian

    Ian Guest

    Thanks Joel

    Joel Kolstad wrote:
    > "Ian" <> wrote in message
    > news:...
    > > "The core's synchronous input control signals
    > > (START, ND, BYPASS, CE) are not registered inside thecore.
    > > It is assumed these will be registered external to the core if
    > > required"
    > >
    > > What is the difference between a core with REGISTERED Input and
    > > one WITHOUT REGISTERED input?

    >
    > It means the control signals mentioned are coming out of a flip-flop that's
    > clocked off the same clock that's running to the core.
    >
    > > Does one have the advantage over the other?

    >
    > Well, if you don't synchronize your control signals to the core's clock, you
    > potentially end up with metastability problems (when you inadvertently
    > violate the set-up and hold times of the core's internal flip-flops) and the
    > core will just generate garabge data for you! Granted, for signals like
    > BYPASS, CE, etc., it'll probably recover sooner or later, but the idea is
    > that without synchronization there's no guarantee the thing works at all.
    >
    > The only disadvantages of the core registering the inputs itself would be
    > that (1) it uses up additionally flip-flops and (2) it introduces another
    > clock cycle of latency. In many cases this is a negligible difference, but
    > since many people already have synchronous control signals running around
    > anyway, Xilinx figures they'll go for the ever-so-slightly higher
    > performance/lower gate count solution.
    >
    > > Would adding a Delay Flip-flop do?

    >
    > Just add a regular old flip-flop. Assuming the core came with a timing
    > constrains file, place and route will automatically, uh... place and route
    > the flip-flops such that the set-up and hold times are met on the control
    > signals.
    >
    > ---Joel
     
    Ian, Jan 17, 2007
    #3
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