related and unrelated logic

Discussion in 'VHDL' started by Szymon Janc, Sep 20, 2007.

  1. Szymon Janc

    Szymon Janc Guest

    "Note that once logic distribution reaches the 99% level through related
    logic packing, this does not mean the device is completely utilized.
    Unrelated logic packing will then begin, continuing until all usable
    LUTs and FFs are occupied. Depending on your timing budget, increased
    levels of unrelated logic packing may adversely affect the overall
    timing performance of your design."

    I'm getting this info durring mapping process. Why does it afect timing
    performance? I've tried to google, but couldn't find an answer..

    --
    Szymon K. Janc
    szymon#janc.int.pl // GG: 1383435
    Szymon Janc, Sep 20, 2007
    #1
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  2. Szymon Janc wrote:
    > "Note that once logic distribution reaches the 99% level through related
    > logic packing, this does not mean the device is completely utilized.

    ....
    > I'm getting this info during mapping process. Why does it affect timing
    > performance?


    A signal takes longer to move through two LUTs than one LUT.
    Check the static timing Fmax to see if it is fast enough.
    If this was a warning rather than an error you may be OK.
    Sounds like the device is nearly full.

    -- Mike Treseler
    Mike Treseler, Sep 20, 2007
    #2
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  3. "Szymon Janc" <szymon@nie_spamuj_mnie.janc.int.pl> wrote in message
    news:fcti12$oa7$...
    > "Note that once logic distribution reaches the 99% level through related
    > logic packing, this does not mean the device is completely utilized.
    > Unrelated logic packing will then begin, continuing until all usable
    > LUTs and FFs are occupied. Depending on your timing budget, increased
    > levels of unrelated logic packing may adversely affect the overall
    > timing performance of your design."


    Basically, the message says it all. The place and route will try and only
    use each LUT for mutiple logic functions if those functions are
    interconnected in the design. However, when all the LUTs are used up it can
    try and squeeze the remaining logic into unused parts of LUTs that hold
    totally unrelated functions. Your timing is likely to be compromised because
    the placement will no longer be optimal and routing delays will be higher.

    At the end of the day, as long as your timing requirements are met, it
    doesn't matter how the design was finally placed or routed.
    David Spencer, Sep 20, 2007
    #3
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