relational operators

Discussion in 'VHDL' started by krithiga81@yahoo.com, Sep 11, 2006.

  1. Guest

    Hello All
    I am using this statement in VHDL

    if ( 0 <= (locklength-nlock) < 1 ) then
    .....

    and there is a compile error

    ncvhdl_p: *E,SEQREL (../PLL_MN100.vhd,518|39): illegal sequence of
    relational operators [7.1] [7.2.2].

    Is there anything wrong in the above statement?

    This works in Verilog.

    Thanks
    krithiga
    , Sep 11, 2006
    #1
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  2. Andy Guest

    You cannot chain logical operators in vhdl.

    In your exampe, 0 <= (locklength - nlock) returns boolean, which you
    are then trying to compare to 1. Or, (locklength - nlock) < 1 returns
    boolean, which you are then trying to compare to 0. Either way, it does
    not work.

    Andy


    wrote:
    > Hello All
    > I am using this statement in VHDL
    >
    > if ( 0 <= (locklength-nlock) < 1 ) then
    > ....
    >
    > and there is a compile error
    >
    > ncvhdl_p: *E,SEQREL (../PLL_MN100.vhd,518|39): illegal sequence of
    > relational operators [7.1] [7.2.2].
    >
    > Is there anything wrong in the above statement?
    >
    > This works in Verilog.
    >
    > Thanks
    > krithiga
    Andy, Sep 11, 2006
    #2
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  3. wrote:

    > Hello All
    > I am using this statement in VHDL
    >
    > if ( 0 <= (locklength-nlock) < 1 ) then
    > ....
    >
    > and there is a compile error
    >
    > ncvhdl_p: *E,SEQREL (../PLL_MN100.vhd,518|39): illegal sequence of
    > relational operators [7.1] [7.2.2].
    >
    > Is there anything wrong in the above statement?


    Yes, it is not valid VHDL. Use this instead:

    IF (0 <= (locklength-nlock)) AND ((locklength-nlock) < 1) THEN

    --
    Paul.
    Paul Uiterlinden, Sep 11, 2006
    #3
  4. Guest

    Hi
    Thanks. It does compile but gives

    Error! simulated time overflow
    File: ../PLL_MN100.vhd, line = 518, pos = 29
    Scope: testbench.dut:$PROCESS_028
    Time: 0 FS + 0

    .../PLL_MN100.vhd:518 if ( 0 <= (locklength-nlock)) AND
    ((locklength-nlock) < 1 ) then

    I have declared locklength and nlock as integer

    Thanks
    krithiga

    Paul Uiterlinden wrote:
    > wrote:
    >
    > > Hello All
    > > I am using this statement in VHDL
    > >
    > > if ( 0 <= (locklength-nlock) < 1 ) then
    > > ....
    > >
    > > and there is a compile error
    > >
    > > ncvhdl_p: *E,SEQREL (../PLL_MN100.vhd,518|39): illegal sequence of
    > > relational operators [7.1] [7.2.2].
    > >
    > > Is there anything wrong in the above statement?

    >
    > Yes, it is not valid VHDL. Use this instead:
    >
    > IF (0 <= (locklength-nlock)) AND ((locklength-nlock) < 1) THEN
    >
    > --
    > Paul.
    , Sep 12, 2006
    #4
  5. wrote:

    > Hi
    > Thanks. It does compile but gives
    >
    > Error! simulated time overflow
    > File: ../PLL_MN100.vhd, line = 518, pos = 29
    > Scope: testbench.dut:$PROCESS_028
    > Time: 0 FS + 0
    >
    > ../PLL_MN100.vhd:518 if ( 0 <= (locklength-nlock)) AND
    > ((locklength-nlock) < 1 ) then
    >
    > I have declared locklength and nlock as integer


    Hmm, that's odd. Could be an error message that does not quite
    indicate the correct position of the actual error.

    Just guessing: perhaps you've used a variable of type time that should
    have been initialized to 0 ns. In that case, use type delay_length in
    stead of time. Initialization to 0 ns is then done automatically, as
    the left bound of delay_length is 0 ns.

    I would suggest to strip down the code to find out where the error
    comes from.
    --
    Paul.
    Paul Uiterlinden, Sep 12, 2006
    #5
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