Relative placement constraints in VHDL for Virtex multipliers

Discussion in 'VHDL' started by Jack Stone, Jul 25, 2003.

  1. Jack Stone

    Jack Stone Guest

    This question may have been asked before but ...

    I often have timing problems when using virtex-II dedicated
    multipliers. After synthesis/P&R I have fixed these by looking at the
    placement with ISE floorplanner and then constraining the multipliers
    and their i/o registers to be packed as close together as possible.
    This requires too much effort for this lazy engineer. I must be
    possible to do this constraining in my VHDL code via attributes. How?
    Does anyone have a bit of example code?

    I don't really want to place the multiplier in any certain spot,
    rather just make sure that the registers holding its input and
    catching its output will be placed in the adjacent slices...

    Thanks in advance for your help.
    Jack Stone, Jul 25, 2003
    #1
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  2. Jack Stone

    Symon Guest

    Jack,
    http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp

    Relationally Placed Macros

    HTH, Syms.

    (Jack Stone) wrote in message news:<>...
    > This question may have been asked before but ...
    >
    > I often have timing problems when using virtex-II dedicated
    > multipliers. After synthesis/P&R I have fixed these by looking at the
    > placement with ISE floorplanner and then constraining the multipliers
    > and their i/o registers to be packed as close together as possible.
    > This requires too much effort for this lazy engineer. I must be
    > possible to do this constraining in my VHDL code via attributes. How?
    > Does anyone have a bit of example code?
    >
    > I don't really want to place the multiplier in any certain spot,
    > rather just make sure that the registers holding its input and
    > catching its output will be placed in the adjacent slices...
    >
    > Thanks in advance for your help.
    Symon, Jul 25, 2003
    #2
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