Repeating Generate loop

Discussion in 'VHDL' started by masoud, Apr 6, 2012.

  1. masoud

    masoud

    Joined:
    Apr 6, 2012
    Messages:
    1
    I want to design a processor that one part of which should be like this

    W(k)=Pre_W(k)-3*W(k-1)
    pre_W(k)=∑x1(i)[x1(i)*W(k-1)+x2(i)*W(k-1)]^3 i=0 to 7

    and my arithmetic operations are all floating point so i should port map them which i cant use process , to perform this I write the code below
    Code:
    for i in 0 to 7 generate 
    s74:multiplier port map (a =>z1(i),b=>w1(0),clk => clk,result =>pre1(i));
    s75:multiplier port map (a =>z2(i),b=>w2(0),clk => clk,result =>pre2(i));
    s76:     adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
    s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
    s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
    s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
    s82:multiplier port map (a =>w1(0),b=>three,clk => clk,result =>nw1(0));
    end generate ;
    
    gen13:for i in 0 to 3 generate 
    s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
    end generate ;
    
    gen14:for i in 0 to 1 generate 
    s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
    end generate ;
    
    --
    s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(0));
    s84:subtractor port map (a =>pre9(0),b=>nw1(0),clk => clk,result =>w1(1));
    which calculates the W1(1) from W1(0) which is a random number to go further W1(2),W1(3), .... by using this code in another generate loop my signals get undefined and code is like this

    Code:
    for j in  0 to 7 generate 
    for i in  0 to 7 generate 
    s74:multiplier port map (a =>z1(i),b=>w1(j),clk => clk,result =>pre1(i));
    s75:multiplier port map (a =>z2(i),b=>w2(j),clk => clk,result =>pre2(i));
    s76:     adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
    s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result =>pre4(i));
    s78:multiplier port map (a =>pre3(i),b=>pre4(i),clk => clk,result =>pre5(i));
    s79:multiplier port map (a =>z1(i),b=>pre5(i),clk => clk,result =>pre6(i));
    s82:multiplier port map (a =>w1(j),b=>three,clk => clk,result =>nw1(j));
    end generate ;
    
    gen13:for i in 0 to 3 generate 
    s80:adder port map (a =>pre6(2*i),b=>pre6((2*i)+1),clk => clk,result =>pre7(i));
    end generate ;
    
    gen14:for i in 0 to 1 generate 
    s81:adder port map (a =>pre7(2*i),b=>pre7((2*i)+1),clk => clk,result =>pre8(i));
    end generate ;
    
    --
    s83:adder port map (a =>pre8(0),b=>pre8(1),clk => clk,result =>pre9(j));
    s84:subtractor port map (a =>pre9(j),b=>nw1(j),clk => clk,result =>w1(j+1));
    end generate ;
    end genarate ;
    masoud, Apr 6, 2012
    #1
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