replacing whens with some kind of for-loop,

Discussion in 'VHDL' started by moberg2236, Feb 18, 2010.

  1. moberg2236

    moberg2236

    Joined:
    Feb 18, 2010
    Messages:
    1
    To be able to make the design i'm working on mor general so it will be easier to change,change the number of inports for example.
    Therefore i would like to replace the code below with a for loop.



    time_out <= inports(0) when id_in_sig = "0000" else
    inports(1) when id_in_sig = "0001" else
    inports(2) when id_in_sig = "0010" else
    inports(3) when id_in_sig = "0011" else
    inports(4) when id_in_sig = "0100" else
    inports(5) when id_in_sig = "0101" else
    inports(7) when id_in_sig = "0111" else
    inports(7) when id_in_sig = "0111" else
    inports(8) when id_in_sig = "1000" else
    inports(9) when id_in_sig = "1001" else
    inports(10) when id_in_sig = "1010" else
    inports(11) when id_in_sig = "1011" else
    inports(12) when id_in_sig = "1100" else
    inports(13) when id_in_sig = "1101" else
    inports(14) when id_in_sig = "1110" else
    inports(15) when id_in_sig = "1111";

    With different variations, i have tested the following for loop


    snurra: for N in 0 to interrupt_in_size generate
    time_out<= inports(N) when id_in_sig = conv_std_logic_vector(N, id_size);

    end generate;

    The problem is now that i cant find a way to make it work in any way, as you see, the for loop will result in that time_out will get assigned multiple values, but i only want it to be set to one value when a certain id_in_sig is set,

    For your information, inports is an array of size 16 of std_logic_vectors (15 downto 0)

    Time out is a std_logic_vector(15 downto 0)
    id_in_sig is a 4 bit id.

    Making a for-loop works for me in every other case, except for this one where i want 1 signal to have 16 possible values depending on the id_sig

    This is not a problem to make my code work, but since figuring this one out, probably could help speeding up my coding i would appreciate any help
     
    moberg2236, Feb 18, 2010
    #1
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  2. moberg2236

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Replacing "whens"

    The code below does essentially what you are trying to do. The function num_bits is in a package I wrote (vhdl_lib_2.arithmetic_pkg).

    --=====================================================================
    library ieee;
    use ieee.std_logic_1164.all;
    --=====================================================================
    package m_to_n_mux_pkg is

    constant mux_in_width : positive := 256; -- m
    constant mux_out_width : positive := 9; -- n

    type vec_array is array(mux_in_width - 1 downto 0) of std_logic_vector(mux_out_width - 1 downto 0);

    component m_to_n_mux
    port( sel : in std_logic_vector;
    mux_in : in vec_array;
    mux_out : out std_logic_vector(mux_out_width - 1 downto 0)
    );
    end component;

    end m_to_n_mux_pkg;
    --=====================================================================
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    library vhdl_lib_2;
    use vhdl_lib_2.arithmetic_pkg.all;
    use work.m_to_n_mux_pkg.all;
    --=====================================================================
    --The num_bits function returns the minimum number of bits required to represent a specified number
    -- of states using binary encoding. For example: num_bits(5) = 3, num_bits(8) = 3, num_bits(9) = 4
    -----------------------------------------------------------------------
    entity m_to_n_mux is
    port( sel : in std_logic_vector(num_bits(mux_in_width) - 1 downt to 0);
    mux_in : in vec_array;
    mux_out : out std_logic_vector(mux_out_width - 1 downto 0)
    );
    end m_to_n_mux;

    architecture arch_mux of m_to_n_mux is

    begin
    pmux : process(mux_in, sel)
    begin
    mux_out <= mux_in(to_integer(unsigned(sel)));
    end process;
    end arch_mux;
     
    eliascm, Feb 18, 2010
    #2
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