report"" in vhdl

Discussion in 'VHDL' started by bedrr, Nov 26, 2007.

  1. bedrr

    bedrr

    Joined:
    Nov 22, 2007
    Messages:
    5
    Location:
    morocco
    does any body know how to display signals values in vhdl?
    I mean the equivalent of $display("message :") &value; in verilog language.
    Bedrr;
    bedrr, Nov 26, 2007
    #1
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