Representing the buffer with logic gates,flipflops

Discussion in 'VHDL' started by KSR, Oct 29, 2009.

  1. KSR

    KSR

    Joined:
    Oct 23, 2009
    Messages:
    12
    Hello all,
    Does anyone tried implementing the an array with logic gates, flipflops in vhdl??
    I f so, can u pls give me idea ...
    ** No need of source code...idea to start..
     
    KSR, Oct 29, 2009
    #1
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  2. KSR

    jeppe

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    Try this page - could give you inspiration:

    jjmk.dk/MMMI/Exercises/05_Counters_Shreg/No4_LIFO_Stack/index.htm
     
    jeppe, Oct 29, 2009
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  3. KSR

    KSR

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    Oct 23, 2009
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    @jeppe,
    i tried to define an array ..As u can see instead of using constant sample i tried to write code such that for every rising edge of clk the array should get filled..

    package arrays is
    type a1 is array (1 to 7) of integer range 0 to 8;

    --constant sample:a1:=(1,2,3,4,5,6,7); to define an array activate this..
    end arrays;

    Library ieee;
    Library work;
    use ieee.std_logic_1164.all;
    use work.arrays.all;

    entity rbf2410 is
    port(i : in integer range 0 to 8;
    clk : in std_logic;
    output : out integer range 0 to 8);
    end rbf2410;

    architecture rbf1 of rbf2410 is
    signal arr : a1;
    begin
    process(clk)
    variable i : integer range 0 to 8;
    begin
    if rising_edge(clk) then
    i:=i+1;
    if (i<7) then
    arr(i)<=i;
    output<=arr(i);
    -- i<=i+1;
    else
    arr(i)<=i;
    output<=arr(i);
    i:=0;
    end if;
    end if;
    end process;
    end rbf1;


    But i am not getting exact o/p in waveform..like there is a delay in o/p
    Can u hav a look at this??
     
    KSR, Oct 29, 2009
    #3
  4. KSR

    jeppe

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    Code:
    Library ieee;
    Library work;
    use ieee.std_logic_1164.all;
    use work.arrays.all;
    
    entity rbf2410 is
          port(i : in integer range 0 to 8;
          clk : in std_logic;
          output : out integer range 0 to ;
    end rbf2410;
    
    architecture rbf1 of rbf2410 is
        -- signal arr : a1;
    begin
        process(clk)
             variable i : integer range 0 to 8;
             variable arr : a1;
        begin
            if rising_edge(clk) then
                 i:=i+1;
                 if (i<7) then
                      arr(i):=i;
                      output<=arr(i);
                      -- i<=i+1;
                 else
                      arr(i):=i;
                      output<=arr(i);
                      i:=0;
                end if;
            end if;
         end process;
    end rbf1;
    this should remove your delay - search the net for the interactive book - EVITA VHDL - chapter 6 will answer you question

    Jeppe
     
    Last edited: Oct 30, 2009
    jeppe, Oct 30, 2009
    #4
  5. KSR

    KSR

    Joined:
    Oct 23, 2009
    Messages:
    12
    @jeppe,

    delay got removed in o/p...and i read e-vita..Thanks for sharing it!!
    heres a quick question..
    i am observed that my o/p is starting with 0 value followed by given input values..dis is because of falling edge of clk..is thr anyway to get rid of dis 0??

    In addition i want to know,
    1)Can we get the values stored in an array ...like wise print statement displaying the values of an array in C??(I am novice to this field donno this is a rite ques. or not)

    2) Can we implement an array without a process statement???


    Thanks,
    KSR.
     
    KSR, Nov 2, 2009
    #5
  6. KSR

    jeppe

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    Location:
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    Hi KSR

    If your code for the purpose of simulation will some the operations be possible - like for instance some of the print like statemens.
    Anyway will a simulator alllow ├Żou to display the content of an array.

    Yes you can use an array without a process. But more "advanced" code will
    take a process to implement.
     
    jeppe, Nov 2, 2009
    #6
  7. KSR

    KSR

    Joined:
    Oct 23, 2009
    Messages:
    12
    can u pls help me in figuring out ring buffer from that array code.
    I tried but my empty, full signals are not incrementing even at clock edge..
    Give me some idea how to start...

    Waiting for reply..
    Kavya.
     
    KSR, Nov 3, 2009
    #7
  8. KSR

    jeppe

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    Whats the entity of your ringbuffer?
     
    jeppe, Nov 3, 2009
    #8
  9. KSR

    KSR

    Joined:
    Oct 23, 2009
    Messages:
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    entity rbf is

    generic (
    B : natural :=8; -- number of bit
    W: natural :=4 -- number of address bit
    );

    port (

    clk, reset : in std_logic;
    rd, wr : in std_logic;
    w_data : in std_logic_vector ( B-1 downto 0);
    empty, full : out std_logic;
    r_data : out std_logic_vector (B-1 downto 0)
    );
    end rbf;

    heres the entity..
    i got code compiled..but when i tried to view waveform by giving input data..output signals r blank(0)..

    Thanks
    KSR
     
    KSR, Nov 3, 2009
    #9
  10. KSR

    jeppe

    Joined:
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    Location:
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    Hi Kavya

    Try this code - I know you wanted hints - but you got some code instead which you can modify for your needs.

    your welcome
    Jeppe

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity rbf is
          generic (
                B : natural :=8; -- number of bit
                W: natural :=4 -- number of address bit
                );
          port ( clk, reset : in std_logic;
                 rd, wr : in std_logic;
                 w_data : in std_logic_vector ( B-1 downto 0);
                 empty, full : inout std_logic;
                 r_data : out std_logic_vector (B-1 downto 0));
    end rbf;
    
    architecture Behavioral of rbf is
       type array_type is array (0 to 2**W-1) of std_logic_vector( B-1 downto 0);
       signal ringbuffer: array_type;
       signal w_index, r_index: std_logic_vector( W-1 downto 0);  --integer range 0 to 2**W-1;
       signal count:            std_logic_vector( W downto 0);
    begin
    
       empty <= '1' when count=0    else '0';
       full  <= '1' when count=2**W else '0';
       r_data <= ringbuffer( conv_integer(r_index));
       
       process( clk)
          variable wr_edge, rd_edge: std_logic_vector( 1 downto 0) := "00";
       begin
          if rising_edge( clk) then
             if reset = '1' then
                w_index <= (others=>'0');
                r_index <= (others=>'0');
                count   <= (others=>'0');
                wr_edge := wr&wr;
                rd_edge := rd&rd;
             else
                if wr_edge="01" and full='0' then
                   ringbuffer( conv_integer(w_index)) <= w_data;
                   w_index <= w_index+1;
                   count   <= count+1;
                end if;
                if rd_edge="01" and empty='0' then
                   r_index <= r_index+1;
                   count <= count-1;
                end if;
                wr_edge := wr_edge(0) & wr;
                rd_edge := rd_edge(0) & rd;
             end if;
          end if;
       end process;
       
    end Behavioral;
     
    jeppe, Nov 3, 2009
    #10
  11. KSR

    KSR

    Joined:
    Oct 23, 2009
    Messages:
    12
    @jeppe,
    Thanks for code.
    i tried to compile it..i think i am not giving correct input values to i/p ports.
    and one more doubt is that u have taken full,empty as inout ports...
    in output waveform they are at Z value.
    Is thr anyway to send my simulation waveform so that u can figure out whts going on worng??

    Thanks,
    KSR
     
    KSR, Nov 5, 2009
    #11
  12. KSR

    jeppe

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    Messages:
    348
    Location:
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    Hi KSR

    I actually simulated and tested the design - TestBench below
    the INOUT signals will not be Z unless you tell it to be so. The INOUT could be substituted with BUFFER if you like.

    Your welcome
    Jeppe

    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;
     
    ENTITY TB_rbf IS
    END TB_rbf;
     
    ARCHITECTURE behavior OF TB_rbf IS 
     
        -- Component Declaration for the Unit Under Test (UUT)
        COMPONENT rbf
        PORT( clk : IN  std_logic;
             reset : IN  std_logic;
             rd : IN  std_logic;
             wr : IN  std_logic;
             w_data : IN  std_logic_vector(7 downto 0);
             empty : INOUT  std_logic;
             full : INOUT  std_logic;
             r_data : OUT  std_logic_vector(7 downto 0)
            );
        END COMPONENT;
        
    
       --Inputs
       signal clk : std_logic := '0';
       signal reset : std_logic := '0';
       signal rd : std_logic := '1';
       signal wr : std_logic := '1';
       signal w_data : std_logic_vector(7 downto 0) := (others => '0');
    
    	--BiDirs
       signal empty : std_logic;
       signal full : std_logic;
    
     	--Outputs
       signal r_data : std_logic_vector(7 downto 0);
    
       -- Clock period definitions
       constant clk_period : time := 10 ns;
    BEGIN
     
      --Instantiate the Unit Under Test (UUT)
       uut: rbf PORT MAP (
              clk => clk,
              reset => reset,
              rd => rd,
              wr => wr,
              w_data => w_data,
              empty => empty,
              full => full,
              r_data => r_data);
    
       -- Clock process definitions
       clk_process :process
       begin
          clk <= '0';
          wait for clk_period/2;
          clk <= '1';
          wait for clk_period/2;
       end process;
    
       -- Stimulus process
       stim_proc: process
       begin	
         reset <= '1';
         wait for clk_period*2;
         reset <= '0';       
         w_data <= "00010000";     
         wait for clk_period*2;
         
         for i in 0 to 17 loop
             w_data <= w_data+1;
             wr <= '0';
             wait for clk_period*2;
             wr <= '1';
             wait for clk_period*2;    
         end loop;
    
         for i in 0 to 17 loop
             rd <= '0';
             wait for clk_period*2;
             rd <= '1';
             wait for clk_period*2;    
         end loop;
          wait;
       end process;
    
    END;
     
    jeppe, Nov 5, 2009
    #12
  13. KSR

    KSR

    Joined:
    Oct 23, 2009
    Messages:
    12
    @jeppe,
    Okay i understood..Thanks..
    Are there any nice books that i can refer for writing testbenches ...becuase i want to learn them..
     
    KSR, Nov 6, 2009
    #13
  14. KSR

    jeppe

    Joined:
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    Location:
    Denmark
    Most books do have chapters of about the topic testbenching.
    But I can't give you a specific title.
    The EVITA gives some hints about delays - My example above will be sufficent for most cases.
     
    jeppe, Nov 6, 2009
    #14
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