Request for Support: VHDL-200X

Discussion in 'VHDL' started by Jim Lewis, Feb 28, 2005.

  1. Jim Lewis

    Jim Lewis Guest

    Hi,
    VHDL 200X is a name generically applied to the next several
    set of VHDL language revisions. The first revision comming
    from the VHDL 200X team is termed "Fast Track" and is due for
    completion some time this year. If you are interested in a
    general overview of what we are doing, see the paper titled,
    "VHDL-200X: The Future of VHDL" that is posted at:
    http://www.synthworks.com/papers/

    The VHDL-200X webpage is at:
    http://www.eda.org/vhdl-200x/

    The VHDL-200X Fast Track webpage is at:
    http://www.eda.org/vhdl-200x/vhdl-200x-ft/


    We need your support. This has mulitple meanings.
    1) Participate.
    Review packages (see my next c.l.v message)
    Review fast track proposals (particularly ones not marked done)
    Join the working group reflectors reflector(s).
    See vhdl-200x page or any of the subgroup working group pages
    Most of the current work is being done under the fast track
    reflector.

    To submit requests for enhancements for future versions of VHDL,
    goto the following webpage or see the link on the left side
    of the vhdl-200x webpage (referenced above):
    http://www.eda.org/vasg/bugrep.htm

    Note: Although the standards are sponsored by IEEE, IEEE
    membership is not required. IEEE rules only require that you
    have a vested interest in the standard - which you have since
    you are reading this on the comp.lang.vhdl reflector.


    2) Talk to your Vendors
    Vendors are reluctant to invest money in features that you
    are not interested in. If you see features you like, let them
    know. Even better send them a priority list of the vhdl-200x-ft
    features that interest you. Your vendor needs to hear from you.
    This is the only way to ensure rapid adoptation of an EDA standard.

    Also see the note below about vendor financial support of the
    LRM editing below.


    3) We particularly need your financial support (particularly corporate)
    Most of the working group is voluntary, however,
    LRM ediging is done as work for hire due to its time consuming nature.
    The current plan is to hire Dr. Peter Ashenden for this work.
    We need around $200K for the short term effort and are seeking
    contributions.

    We currently have been promised financial support from Mentor and
    Cadence. We are also seeking support from other EDA and FPGA vendors.

    To contribute to this effort, please contact the
    VASG (VHDL Analysis and Standardization Group) chair, Stephen Bailey,
    at

    Best Regards,
    Jim Lewis
    Fast Track Co-Team Leader
    VASG vice chair
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, Feb 28, 2005
    #1
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