Requesting for an Actel library

Discussion in 'VHDL' started by irfan.mohammed@gmail.com, Jun 9, 2006.

  1. Guest

    Hi ,

    I am a student in T.U Braunschweig (in Germany). I am new in VHDL and
    want to implement a project. I am working on VHDL with Actel Libero.
    In my previous implementation, I have used the "RAMB4_S1_S1"(4K-Bit
    Data Dual Port Block RAM) and "RAMB4_S1"(4K-Bit Data Single Port Block
    RAM) which are implemented in the "UNISIM" in Xilinx.
    Could you please provide me with the information of an equivalent
    library that implement these RAMs in Actel Libero ?

    Thanks in advance

    Best regards
    Adamou
     
    , Jun 9, 2006
    #1
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  2. D Stanford Guest


    > Could you please provide me with the information of an equivalent
    > library that implement these RAMs in Actel Libero ?


    You'd probably be better off doing a behavioral design of the RAM so
    that switching target FPGAs does not break things again.
     
    D Stanford, Jun 9, 2006
    #2
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  3. Jeremy Ralph Guest

    Creating technology independent, behavioural RAM models as Stanford
    suggested is a good idea.

    Another good practice is to create generic RAM wrappers which share a
    common entity declaration. Then you can have different architectures
    for behavioural modelling and specific library technologies. You can
    use VHDL configuration files to select the architecture without having
    to change existing code. Thus, if you were to switch to a different
    FPGA or library vendor all you need to do is create an architecture
    that wraps that vendor's RAM instance and glues it to your generic
    RAM interface.

    Unfortunately I can't provide you with any info on Actel Libero RAMs as
    I don't know much about that.

    Hope this helps,
    Jeremy

    PS Braunschweig is a nice town -- I was there once on a work assignment
    (for a large US company which has a site there), coding Verilog though
    rather than VHDL.


    ---
    PDTi [ http://www.productive-eda.com ]
    SpectaReg -- Spec-down code and doc generation for register maps



    wrote:
    > Hi ,
    >
    > I am a student in T.U Braunschweig (in Germany). I am new in VHDL and
    > want to implement a project. I am working on VHDL with Actel Libero.
    > In my previous implementation, I have used the "RAMB4_S1_S1"(4K-Bit
    > Data Dual Port Block RAM) and "RAMB4_S1"(4K-Bit Data Single Port Block
    > RAM) which are implemented in the "UNISIM" in Xilinx.
    > Could you please provide me with the information of an equivalent
    > library that implement these RAMs in Actel Libero ?
    >
    > Thanks in advance
    >
    > Best regards
    > Adamou
     
    Jeremy Ralph, Jun 10, 2006
    #3
  4. Hi,

    schrieb:
    > I am a student in T.U Braunschweig (in Germany). I am new in VHDL and
    > want to implement a project. I am working on VHDL with Actel Libero.
    > In my previous implementation, I have used the "RAMB4_S1_S1"(4K-Bit
    > Data Dual Port Block RAM) and "RAMB4_S1"(4K-Bit Data Single Port Block
    > RAM) which are implemented in the "UNISIM" in Xilinx.
    > Could you please provide me with the information of an equivalent
    > library that implement these RAMs in Actel Libero ?


    Actgen is the name of the actel core generator, just use the generated
    core. A second way would be a look in your libray macro cell
    documentation.

    bye Thomas
     
    Thomas Stanka, Jun 12, 2006
    #4
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