Reset Logic Function

Discussion in 'VHDL' started by We Ech Dee Ell, Oct 8, 2010.

  1. Hi All,

    I have some code that consistently gives the problem of "Reset Logic
    Function", "Multiple Resets" etc. with some design checking tool for
    synthesis.


    The code is:
    ------------------


    write_enable : PROCESS (Clock)
    BEGIN
    IF (Clock'EVENT) AND (Clock = '1') THEN
    IF ( Reset = '1' ) THEN
    register_we_REG1_i1 <= '0';
    Wack <= '0';
    ELSIF (WStrobe = '1') THEN
    register_we_REG1_i1 <= register_select(0);
    Wack <= '1';
    END IF;
    END IF;
    END PROCESS write_enable;

    ----------------------------------------------------------------
    reg_REG1_field16_i1 : PROCESS (Clock)
    BEGIN
    IF (Clock'EVENT) AND (Clock = '1') THEN
    IF Reset = '1' THEN
    field16_i1 <= '1';
    ELSIF ( register_we_REG1_i1 = '1' ) THEN
    field16_i1 <= Wdata(16);
    END IF;
    END IF;
    END PROCESS reg_REG1_field16_i1;


    Can someone please help?
    Change is sensitivity lists is not allowed. Only synchronous processes
    are allowed.


    Thanks a lot in advance!
    We Ech Dee Ell, Oct 8, 2010
    #1
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  2. We Ech Dee Ell

    backhus Guest

    On 8 Okt., 10:53, We Ech Dee Ell <> wrote:
    > Hi All,
    >
    > I have some code that consistently gives the problem of "Reset Logic
    > Function", "Multiple Resets" etc. with some design checking tool for
    > synthesis.
    >
    > The code is:
    > ------------------
    >
    >  write_enable : PROCESS (Clock)
    >   BEGIN
    >     IF (Clock'EVENT) AND (Clock = '1') THEN
    >       IF ( Reset = '1' ) THEN
    >           register_we_REG1_i1 <= '0';
    >           Wack <= '0';
    >       ELSIF (WStrobe = '1') THEN
    >           register_we_REG1_i1 <= register_select(0);
    >           Wack <= '1';
    >       END IF;
    >     END IF;
    >   END PROCESS write_enable;
    >
    >  ----------------------------------------------------------------
    >   reg_REG1_field16_i1 : PROCESS (Clock)
    >   BEGIN
    >     IF (Clock'EVENT) AND (Clock = '1') THEN
    >       IF Reset = '1' THEN
    >         field16_i1 <= '1';
    >       ELSIF ( register_we_REG1_i1 = '1' ) THEN
    >         field16_i1 <= Wdata(16);
    >       END IF;
    >     END IF;
    >   END PROCESS reg_REG1_field16_i1;
    >
    > Can someone please help?
    > Change is sensitivity lists is not allowed. Only synchronous processes
    > are allowed.
    >
    > Thanks a lot in advance!


    Hi,
    the code shows some nice examples for FFs with sync. Reset and Clock
    Enable functions.
    Only thing that looks strange to me is the Wack signal, that never
    returns to '0', unless the FF gets resetted.
    Once written to the FF, the write acknowledge never becomes inactive?
    If not really intended an else branch could fix this.

    So, what about the mentioned reset problem?
    What messages do you see, printed by what kind of tool?
    I can't see a connection between your code fragments and the very
    common prased problems.

    Have a nice synthesis
    Eilert
    backhus, Oct 11, 2010
    #2
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