Reset Logic Function

Discussion in 'VHDL' started by We Ech Dee Ell, Oct 8, 2010.

  1. Hi All,

    I have some code that consistently gives the problem of "Reset Logic
    Function", "Multiple Resets" etc. with some design checking tool for
    synthesis.


    The code is:
    ------------------


    write_enable : PROCESS (Clock)
    BEGIN
    IF (Clock'EVENT) AND (Clock = '1') THEN
    IF ( Reset = '1' ) THEN
    register_we_REG1_i1 <= '0';
    Wack <= '0';
    ELSIF (WStrobe = '1') THEN
    register_we_REG1_i1 <= register_select(0);
    Wack <= '1';
    END IF;
    END IF;
    END PROCESS write_enable;

    ----------------------------------------------------------------
    reg_REG1_field16_i1 : PROCESS (Clock)
    BEGIN
    IF (Clock'EVENT) AND (Clock = '1') THEN
    IF Reset = '1' THEN
    field16_i1 <= '1';
    ELSIF ( register_we_REG1_i1 = '1' ) THEN
    field16_i1 <= Wdata(16);
    END IF;
    END IF;
    END PROCESS reg_REG1_field16_i1;


    Can someone please help?
    Change is sensitivity lists is not allowed. Only synchronous processes
    are allowed.


    Thanks a lot in advance!
    We Ech Dee Ell, Oct 8, 2010
    #1
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