Reseting on an edge or one-shot

Discussion in 'VHDL' started by Steven Menk, Feb 13, 2006.

  1. Steven Menk

    Steven Menk Guest

    I have a state machine where I need to reset with asyncronise signal
    but don't want to wait I have a state machine where I need to reset
    with asynchronous signal but don't want to wait for that signal to go
    back low before the machine goes out of its initial state. In other
    words I'd like to reset either on the edge or during the first clock
    cycle in which the reset is high and continue to run until it goes low
    then back high again...

    How would I go about doing this?

    Thanks.
     
    Steven Menk, Feb 13, 2006
    #1
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  2. Steven Menk

    Steven Menk Guest

    Sorry. I screwed up when cutting and pasting from Word:

    I have a state machine where I need to reset
    with asynchronous signal but don't want to wait for that signal to go
    back low before the machine goes out of its initial state. In other
    words I'd like to reset either on the edge or during the first clock
    cycle in which the reset is high and continue to run until it goes low
    then back high again...

    How would I go about doing this?


    Thanks.
     
    Steven Menk, Feb 13, 2006
    #2
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  3. Steven Menk wrote:

    > I have a state machine where I need to reset
    > with asynchronous signal but don't want to wait for that signal to go
    > back low before the machine goes out of its initial state. In other
    > words I'd like to reset either on the edge or during the first clock
    > cycle in which the reset is high and continue to run until it goes low
    > then back high again...
    >
    > How would I go about doing this?


    I would start by drawing typical input
    and expected output waveforms on a clock grid.
    Then I would name and fill in the internal
    state values at each clock tick.

    -- Mike Treseler
     
    Mike Treseler, Feb 13, 2006
    #3
  4. Steven Menk

    Steven Menk Guest

    That's the problem. The signals are completely asyncronous. The only
    thing that is given is that the reset signal will be at least 3 clk
    cycles long. Other then that the timing and edge relationships are
    completely arbitrary.

    What I ended up doing is taking two D flip-flops, hooking the reset
    signal to the input of the first, and the input of the second to the
    output of the first:

    ARST -> D0 Q0 -> D1 Q1 ->
    clk -> CLK
    -> CLK

    For the reset signal I said:

    RST <= Q0 and not Q1.

    Then:

    process(clk, RST)
    begin
    if RST = '1' then
    CS <= S0;
    elsif clk = '1' and clk'event then
    CS <= NS;
    end if;
    end process;

    Seems to work, but I have a lot more testing to do. Always fun to see
    something work 2 millions times in a row, but break on the
    2,000,001st...
     
    Steven Menk, Feb 14, 2006
    #4
  5. Steven Menk

    Zara Guest

    On 13 Feb 2006 18:39:40 -0800, "Steven Menk" <>
    wrote:

    >
    >ARST -> D0 Q0 -> D1 Q1 ->
    >clk -> CLK
    > -> CLK
    >
    >For the reset signal I said:
    >
    >RST <= Q0 and not Q1.


    But now this reset is synchronous!

    >
    >Then:
    >
    >process(clk, RST)
    >begin
    > if RST = '1' then
    > CS <= S0;
    > elsif clk = '1' and clk'event then
    > CS <= NS;
    > end if;
    >end process;


    So the following is more correc:

    process(clk)
    begin
    if rising_edge(clk) then
    if rst='1' then
    CS <= S0;
    else
    CS <= NS;
    end if;
    end if;
    end process;


    Best regards,

    Zara
     
    Zara, Feb 14, 2006
    #5
  6. Steven Menk

    Steven Menk Guest

    Wouldn't that give me a race condition? My RST will go high on one
    rising edge of clk then low on the next.
     
    Steven Menk, Feb 14, 2006
    #6
  7. Steven Menk

    Zara Guest

    On 14 Feb 2006 06:09:25 -0800, "Steven Menk" <>
    wrote:

    >Wouldn't that give me a race condition? My RST will go high on one
    >rising edge of clk then low on the next.


    From your previous message:

    >
    >ARST -> D0 Q0 -> D1 Q1 ->
    >clk -> CLK
    > -> CLK
    >
    >For the reset signal I said:
    >
    >RST <= Q0 and not Q1.



    So I deduce you are synchronizing reeset signal by sampling it (Q0),
    and then delaying it by one cycle (Q1). The new RST signal appears
    only on the rising edge of ARST, so there should be no race condition,
    unless ARST is toggling. But in such case, the reset pulses would be
    OK, as they meet the specificationos of OP

    Best regards,

    Zara
     
    Zara, Feb 15, 2006
    #7
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