Resetting FIFO

Discussion in 'VHDL' started by ALuPin, Feb 9, 2005.

  1. ALuPin

    ALuPin Guest

    Hi,
    maybe someone can give her/his opinion concerning the following question:
    Thank you in advance.


    I have a FIFO template with one write clock and one read clock. These
    clocks are full asynchronous to each other.

    Apart from that I have an asynchronous reset port in the FIFO.

    My question:

    Let us assume that I sychronize the asynchronous reset coming from FPGA
    input pin
    in a flip flop chain to synchronize it to the write clock

    and in a second flip flop chain to synchronize it to the read clock.

    Which synchronized reset do I have to use
    to reset the FIFO in a safe manner ?

    Rgds
    André
     
    ALuPin, Feb 9, 2005
    #1
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  2. ALuPin

    Gabor Guest

    ALuPin wrote:
    > Hi,
    > maybe someone can give her/his opinion concerning the following

    question:
    > Thank you in advance.
    >
    >
    > I have a FIFO template with one write clock and one read clock. These
    > clocks are full asynchronous to each other.
    >
    > Apart from that I have an asynchronous reset port in the FIFO.
    >
    > My question:
    >
    > Let us assume that I sychronize the asynchronous reset coming from

    FPGA
    > input pin
    > in a flip flop chain to synchronize it to the write clock
    >
    > and in a second flip flop chain to synchronize it to the read clock.
    >
    > Which synchronized reset do I have to use
    > to reset the FIFO in a safe manner ?


    Really the FIFO design needs to handle synchronizing the single
    async input to both clocks internally. I would suggest synchronizing
    to the write clock and then making sure your write logic stays
    quiescent (doesn't start writing) for a few cycles after reset in
    case the FIFO hasn't finished resetting the read state logic. In
    the Xilinx COREgen designs, reset asserts both FULL and EMPTY, which
    effectively prevents reads or writes during the reset condition
    and until each of these signals de-asserts synchronously to its
    respective clock.

    >
    > Rgds
    > André
     
    Gabor, Feb 9, 2005
    #2
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