Retaining not used nodes

Discussion in 'VHDL' started by ALuPin, Feb 8, 2005.

  1. ALuPin

    ALuPin Guest

    Hi,

    I have several nodes in my design (registered nodes) which do not have
    a "driving" purpose. But for later use of SignalTap (Altera tool to
    make internal FPGA nodes visible) I do want the synthesizer
    not to optimize these nodes away. On the other hand I do not want
    to route these nodes to output pins because of a limited amount of
    available pins.

    Is there some possibility to avoid that these registerd not used nodes
    are optimized away ?

    Thank you for your suggestion.

    Rgds
    André
     
    ALuPin, Feb 8, 2005
    #1
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  2. ALuPin

    mk Guest

    On 8 Feb 2005 02:43:57 -0800, (ALuPin) wrote:

    >Hi,
    >
    >I have several nodes in my design (registered nodes) which do not have
    >a "driving" purpose. But for later use of SignalTap (Altera tool to
    >make internal FPGA nodes visible) I do want the synthesizer
    >not to optimize these nodes away. On the other hand I do not want
    >to route these nodes to output pins because of a limited amount of
    >available pins.
    >
    >Is there some possibility to avoid that these registerd not used nodes
    >are optimized away ?
    >
    >Thank you for your suggestion.
    >
    >Rgds
    >André


    There are synthesis pragmas which you can use to keep these registers
    (syn_keep for synplicity etc.). If you have too much difficulty
    convincing either the synthesizer or the mapper to keep these unused
    registers, you can "or" the outputs of multiple registers and route it
    to a single output pin which should vastly reduce your pin
    availability concerns.
     
    mk, Feb 8, 2005
    #2
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  3. ALuPin

    Christos Guest

    Hi,

    One thing that might work is to drive them to outputs and then define those
    outputs as virtual pins with the assignment editor.
    They will not be synthesised away.

    hope this helps.

    Christos Zamantzas

    "mk" <kal*@dspia.*comdelete> wrote in message
    news:...
    > On 8 Feb 2005 02:43:57 -0800, (ALuPin) wrote:
    >
    > >Hi,
    > >
    > >I have several nodes in my design (registered nodes) which do not have
    > >a "driving" purpose. But for later use of SignalTap (Altera tool to
    > >make internal FPGA nodes visible) I do want the synthesizer
    > >not to optimize these nodes away. On the other hand I do not want
    > >to route these nodes to output pins because of a limited amount of
    > >available pins.
    > >
    > >Is there some possibility to avoid that these registerd not used nodes
    > >are optimized away ?
    > >
    > >Thank you for your suggestion.
    > >
    > >Rgds
    > >André

    >
    > There are synthesis pragmas which you can use to keep these registers
    > (syn_keep for synplicity etc.). If you have too much difficulty
    > convincing either the synthesizer or the mapper to keep these unused
    > registers, you can "or" the outputs of multiple registers and route it
    > to a single output pin which should vastly reduce your pin
    > availability concerns.
    >
     
    Christos, Feb 8, 2005
    #3
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