RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

Discussion in 'VHDL' started by Jim Lewis, Mar 29, 2007.

  1. Jim Lewis

    Jim Lewis Guest

    Hi,
    The VHDL standards community needs feedback from VHDL users.

    Currently the Accellera VHDL TSC is working on enhancements
    to add classes/OO, Randomization constructs, and Functional
    Coverage with a goal of giving VHDL the same verification
    capability as SystemVerilog or E.

    One of the VHDL simulation vendors has indicated that they
    only want to implement new features if the user community
    wants these features.

    The questions come down to:
    Do you want these features added to VHDL?
    Do you want to VHDL to be capable of handling all of your
    testbench needs?

    This work is work in progress and below is the current status.
    Keep in mind too that your interest/support of this work will
    help raise the focus and inspiration of those doing the work.

    Classes / OO:
    Peter Ashenden submitted a class proposal last year and
    provided updates to it this year at DVCon. Currently
    he plans on finishing an updated draft soon.

    Randomization:
    I just submitted the first draft of the randomization proposal.

    Functional Coverage:
    I have started working on this - anyone else who is interested
    is welcome to contribute as much as they would like.


    With a focused effort, like the one to finish the Accellera 3.0
    draft of the standard, I think we can be done with these by
    September.

    Although some have expressed doubt, it is clear that vendors
    will do what their user community asks them to do - otherwise,
    someone else will and, as a result, will earn your business.

    You can post here, send your reply to me (let me know if I can use
    either your name and/or company name when I tally the results
    for the Accellera VHDL TSC), or join the Accellera VHDL TSC
    (which you can do as a non-Accellera member by registering)
    and post your reply there.

    Thanks,
    Jim Lewis
    VHDL Evangelist
    SynthWorks VHDL Training
     
    Jim Lewis, Mar 29, 2007
    #1
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  2. Jim Lewis

    Amal Guest

    Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

    On Mar 29, 5:51 pm, Jim Lewis <> wrote:
    > Hi,
    > The VHDL standards community needs feedback from VHDL users.
    >
    > Currently the Accellera VHDL TSC is working on enhancements
    > to add classes/OO, Randomization constructs, and Functional
    > Coverage with a goal of giving VHDL the same verification
    > capability as SystemVerilog or E.
    >
    > One of the VHDL simulation vendors has indicated that they
    > only want to implement new features if the user community
    > wants these features.
    >
    > The questions come down to:
    > Do you want these features added to VHDL?
    > Do you want to VHDL to be capable of handling all of your
    > testbench needs?
    >
    > This work is work in progress and below is the current status.
    > Keep in mind too that your interest/support of this work will
    > help raise the focus and inspiration of those doing the work.
    >
    > Classes / OO:
    > Peter Ashenden submitted a class proposal last year and
    > provided updates to it this year at DVCon. Currently
    > he plans on finishing an updated draft soon.
    >
    > Randomization:
    > I just submitted the first draft of the randomization proposal.
    >
    > Functional Coverage:
    > I have started working on this - anyone else who is interested
    > is welcome to contribute as much as they would like.
    >
    > With a focused effort, like the one to finish the Accellera 3.0
    > draft of the standard, I think we can be done with these by
    > September.
    >
    > Although some have expressed doubt, it is clear that vendors
    > will do what their user community asks them to do - otherwise,
    > someone else will and, as a result, will earn your business.
    >
    > You can post here, send your reply to me (let me know if I can use
    > either your name and/or company name when I tally the results
    > for the Accellera VHDL TSC), or join the Accellera VHDL TSC
    > (which you can do as a non-Accellera member by registering)
    > and post your reply there.
    >
    > Thanks,
    > Jim Lewis
    > VHDL Evangelist
    > SynthWorks VHDL Training


    I have been a long time for Classes/OO, Randomization and Functional
    coverage that is already part of SystemVerilog. VHDL is my favorite
    HDL and I think it has always had very high-level constructs ahead of
    its time. The VHDL-2006 is a much needed update, but still comes
    short of the features that SystemVerilog boasts for verification. I
    think Classes/OO is great for synthesis as well and brings the
    language to higher abstraction level that is already enjoyed by
    software developers.

    It is a shame that (big) vendors are pushing SystemVerilog and think
    that there is not enough customer base for VHDL. I beg to differ and
    have be anxiously waiting for VHDL update and OO, verification
    extensions.

    I do not want to start language wars, but take a good look at table on
    page () of the following article and you would agree that VHDL has
    been at higher-level of abstraction than Verilog.
    http://www.edn.com/contents/images/376625t1.pdf

    Verilog is still good for gate-level descriptions and with Verilog
    2001 extensions they brought it up to par with VHDL, and then
    SystemVerilog extensions added more features to get market share from
    Verisity and E supporters by pushing a supposedly standard driven
    language. Although we all know the big vendor influence.

    I hope these proposed features and the good works of Peter, Jim and
    other drivers of this great language is not taken for granted.

    -- Amal
     
    Amal, Mar 30, 2007
    #2
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  3. Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

    Hi Jim,

    On 29 Mrz., 23:51, Jim Lewis <> wrote:
    > The VHDL standards community needs feedback from VHDL users.
    >
    > Currently the Accellera VHDL TSC is working on enhancements
    > to add classes/OO, Randomization constructs, and Functional
    > Coverage with a goal of giving VHDL the same verification
    > capability as SystemVerilog or E.
    >
    > One of the VHDL simulation vendors has indicated that they
    > only want to implement new features if the user community
    > wants these features.


    And I guess mti won't support these features with Modelsim, to force
    Questa sells, like it is with SV. This might be a major issue when it
    comes to market usage.

    > The questions come down to:
    > Do you want these features added to VHDL?


    Don't know if OO-update is a good idea to a language, but we will see.
    C++ is not the best idea for OO IMHO because it relays to much on
    procedural statements. VHDL has no choice, when it comes to procedural
    statements.

    But I would realy appreciate, if vdhl would support built-in "modern"
    assertions like PSL or e.

    > Do you want to VHDL to be capable of handling all of your
    > testbench needs?


    Yes I like VHDL to be enhanced for tomorrows tb needs.
    I am currently working on a design, with included ADC. I have the
    netlist with ADC as blackbox for some purpose, the netlist with
    behavioral model for other purpose. In some cases I need to use
    another library element for a digital gate, than normal. Netlist and
    and one testbench are verilog and it is a pain to select the
    corresponding tb-gtl-library settings without configurations(is no
    porblem using configurations).

    bye Thomas
     
    Thomas Stanka, Mar 30, 2007
    #3
  4. Jim Lewis

    Ben Jones Guest

    Re: Enhancing VHDL for OO, Randomization, Functional Coverage

    Hi Jim,

    "Jim Lewis" <> wrote in message
    news:...
    > Hi,
    > The VHDL standards community needs feedback from VHDL users.
    >
    > Currently the Accellera VHDL TSC is working on enhancements
    > to add classes/OO, Randomization constructs, and Functional
    > Coverage with a goal of giving VHDL the same verification
    > capability as SystemVerilog or E.
    >
    > One of the VHDL simulation vendors has indicated that they
    > only want to implement new features if the user community
    > wants these features.
    >
    > The questions come down to:
    > Do you want these features added to VHDL?
    > Do you want to VHDL to be capable of handling all of your
    > testbench needs?


    I have been looking at SystemVerilog recently, although I am a die-hard VHDL
    guy at heart.

    My wish-list for VHDL, in a prioritized summary, looks something like this.
    There are several language features I think I would rate as more important
    than the verification-related ones you mention:

    (1) Synthesizable fixed/floating-point types for arithmetic datapaths. ISTR
    this being pretty much done now, modulo certain tools supporting it (ahem).

    (2) Types as generics, a.k.a. templates - so one can write e.g. FIFO logic
    which is completely type-agnostic. This flexibility would make code reuse in
    VHDL approximately 10 times easier than it is today.

    (3) Interfaces. Lots of people are coming around to using record types to
    bundle related signals together when interfacing components together. This
    is currently a biy kludgey as it requires separate bundles for each
    direction. I remember seeing a pretty acceptable proposal for properly
    adding this functionality to VHDL.

    (4) Object-orientation. I must look at this Ashenden stuff. The ability to
    create class hierarchies of VHDL components would be another great boost for
    code re-use - particularly in a language where abstraction by
    interface/implementation separation is so prominent.

    (5) Make std_logic_unsigned, std_logic_signed and std_logic_arith into
    reserved words so they are invalid as library names ;-)

    (6) Improved assertions, like SystemVerilog. VHDL assertions are pretty
    limited and hard to use as they stand.

    (7) Binary file I/O that is portable.

    (8) Constrained randomization, like SystemVerilog. Although personally I
    have found procedural randomization to be perfectly adequate in most
    contexts, that's probably just because of the projects I've worked on. I can
    see how this could be a very useful feature.

    (9) Native functional coverage support, like SystemVerilog. This is
    progressively more important as the system being verified gets bigger, but
    it's certainly possible to manage without it.

    There are a few other things that bug me, which I might as well add while
    I'm on a roll:

    (10) Fix the operator precedence rules so they make sense.

    (11) Extend the mandatory range of integers to 64-bit representation, and
    force implementors to support the full range of 2's complement values rather
    than just [-2**N-1 .. 2**N-1]. Not being able to treat VHDL's 32-bit
    "integer" as being the same as C's 32-bit "int" is a royal pain.

    (12) Allow bitwise operations (masks, shifts, rotates, xors etc) on
    integers.

    (13) Include a pre-processor for conditional compilation.

    That's probably enough for now! :)

    Basically I think verification is important, but having a language which
    facilitates good design is more important still. I would prefer to be able
    to do the verification in the same language that I do the design. And I
    would prefer that language to be VHDL!

    Cheers,

    -Ben-
     
    Ben Jones, Mar 30, 2007
    #4
  5. Jim Lewis

    Jim Lewis Guest

    Re: Enhancing VHDL for OO, Randomization, Functional Coverage

    All,
    If you want to continue to have good vendor support for VHDL,
    you need to step up and voice your opinion, even if it is just
    to say that you want these features in VHDL.

    Ben,
    > My wish-list for VHDL, in a prioritized summary, looks something like this.
    > There are several language features I think I would rate as more important
    > than the verification-related ones you mention:
    >
    > (1) Synthesizable fixed/floating-point types for arithmetic datapaths. ISTR
    > this being pretty much done now, modulo certain tools supporting it (ahem).


    In Accellera VHDL standard 3.0 (standardized July 2006 by Accellera)
    available through Accellera.org. Ask your favorite vendors to implement it.

    > (2) Types as generics, a.k.a. templates - so one can write e.g. FIFO logic
    > which is completely type-agnostic. This flexibility would make code reuse in
    > VHDL approximately 10 times easier than it is today.


    In Accellera VHDL standard 3.0. Ask your favorite vendors to implement it.

    > (3) Interfaces. Lots of people are coming around to using record types to
    > bundle related signals together when interfacing components together. This
    > is currently a biy kludgey as it requires separate bundles for each
    > direction. I remember seeing a pretty acceptable proposal for properly
    > adding this functionality to VHDL.


    Me too. I made the initial proposal. I will revisit it after we finish
    classes, randomization, and functional coverage - however to do this
    we need people to voice their opinion.

    > (4) Object-orientation. I must look at this Ashenden stuff. The ability to
    > create class hierarchies of VHDL components would be another great boost for
    > code re-use - particularly in a language where abstraction by
    > interface/implementation separation is so prominent.
    >
    > (5) Make std_logic_unsigned, std_logic_signed and std_logic_arith into
    > reserved words so they are invalid as library names ;-)


    Don't we all wish, but even if it was in the standard,
    vendors would still have to provide a way to allow old designs.

    > (6) Improved assertions, like SystemVerilog. VHDL assertions are pretty
    > limited and hard to use as they stand.


    PSL is integrated into VHDL in Accellera VHDL standard 3.0.
    Ask your favorite vendors to implement it.

    > (7) Binary file I/O that is portable.
    >
    > (8) Constrained randomization, like SystemVerilog. Although personally I
    > have found procedural randomization to be perfectly adequate in most
    > contexts, that's probably just because of the projects I've worked on. I can
    > see how this could be a very useful feature.


    Keep in mind there is a new version due soon.

    > (9) Native functional coverage support, like SystemVerilog. This is
    > progressively more important as the system being verified gets bigger, but
    > it's certainly possible to manage without it.
    >
    > There are a few other things that bug me, which I might as well add while
    > I'm on a roll:
    >
    > (10) Fix the operator precedence rules so they make sense.
    >
    > (11) Extend the mandatory range of integers to 64-bit representation, and
    > force implementors to support the full range of 2's complement values rather
    > than just [-2**N-1 .. 2**N-1]. Not being able to treat VHDL's 32-bit
    > "integer" as being the same as C's 32-bit "int" is a royal pain.
    >
    > (12) Allow bitwise operations (masks, shifts, rotates, xors etc) on
    > integers.
    >
    > (13) Include a pre-processor for conditional compilation.
    >
    > That's probably enough for now! :)
    >
    > Basically I think verification is important, but having a language which
    > facilitates good design is more important still. I would prefer to be able
    > to do the verification in the same language that I do the design. And I
    > would prefer that language to be VHDL!
    >
    > Cheers,
    >
    > -Ben-
    >
    >
     
    Jim Lewis, Mar 30, 2007
    #5
  6. Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

    Hi Jim,

    On 29 Mrz., 23:51, Jim Lewis <> wrote:
    > Currently the Accellera VHDL TSC is working on enhancements
    > to add classes/OO, Randomization constructs, and Functional
    > Coverage with a goal of giving VHDL the same verification
    > capability as SystemVerilog or E.
    >
    > One of the VHDL simulation vendors has indicated that they
    > only want to implement new features if the user community
    > wants these features.


    I just started with VHDL two months ago and I have to say that I find
    it frustrating that I keep running into unimplemented parts of the
    VHDL standard. That's with the Xilinx toolchain and I read a lot of
    that already that I can confirm. A few days before I tried to model a
    ADC wrt. the timing constraints and had to notice that the Xilinx ISE
    Simulator (non ModelSim :() does not support the stable attribute.

    Okay, enough of the rant, what I wanted to say is that I'd expect the
    implementations to conform to the standard.

    > Classes / OO:
    > Peter Ashenden submitted a class proposal last year and
    > provided updates to it this year at DVCon. Currently
    > he plans on finishing an updated draft soon.


    I'd really like to see that proposal. Coming from software development
    it really seems logical to apply OO to HDLs.

    > Randomization:
    > I just submitted the first draft of the randomization proposal.


    Also very interesting, we will need pseudo random data for our project
    as well. Some kind of LFSR will be good enough but having it directly
    supported would be nice, also for synthesis. I can dream, right :)

    > You can post here, send your reply to me (let me know if I can use
    > either your name and/or company name when I tally the results
    > for the Accellera VHDL TSC), or join the Accellera VHDL TSC
    > (which you can do as a non-Accellera member by registering)
    > and post your reply there.


    While I am just starting with VHDL, I'd like to contribute. In fact, I
    became member of IEEE-SA just for that. I figured following that
    discussion would also be the best way to learn VHDL, just as my
    involvement with Debian GNU/Linux as a developer was a real boost for
    my Linux know how. However, I don't think my company is interested in
    spending money and developer time on it so I could only use my spare
    time for it.

    Greetings, Torsten
     
    Torsten Landschoff, Apr 3, 2007
    #6
  7. Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

    Hi Jim,

    I just noticed that I did not really answer your questions, therefore
    I'll try again :)

    On 29 Mrz., 23:51, Jim Lewis <> wrote:

    > The questions come down to:
    > Do you want these features added to VHDL?
    > Do you want to VHDL to be capable of handling all of your
    > testbench needs?
    > [...]
    >
    > Classes / OO:
    > Peter Ashenden submitted a class proposal last year and
    > provided updates to it this year at DVCon. Currently
    > he plans on finishing an updated draft soon.


    Yes, classes/OO would be very welcome.

    > Randomization:
    > I just submitted the first draft of the randomization proposal.


    Same for randomization.

    > Functional Coverage:
    > I have started working on this - anyone else who is interested
    > is welcome to contribute as much as they would like.


    Everybody should want coverage tests as it is important for
    correctness. I am not sure though how this will require language
    changes?

    And of course I'd like to use only VHDL for our test benches. Tcl and
    VHDL kind of works but is not as portable and standardized.

    Greetings, Torsten

    PS: I am working for nAmbition GmbH but any opinions given above are
    my own. Feel free to use my name.
     
    Torsten Landschoff, Apr 3, 2007
    #7
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