Ripple chain logic in VHDL

[Govinda]

Hi,

What is the best way to write a vhdl code for the following encoded logic?

If there is a 4 bit register and you only need to select the first '1' in that register starting from LSB and set all others to zero, how can that be written up in VHDL? I need to do this for a 32 bit register and I cant believe writing up the whole logic (one huge concurrent statement for each bit, especially the MSBs) is the best way to do it. Can anyone here suggest any alternatives?

eg: 1011 needs to be 0001
1100 needs to be 0100
1110 needs to be 0010 etc.


Thanks a lot- any help would be greatly appreciated.

Govinda

 

[jeppe]

Hi

Could it be a carry lookahead adder ?

Any way can you find inspiration at this page -
specially to "for-loop based" version.
http://www.jjmk.dk/MMMI/Lessons/06_Arithmetics/No1_Adders/CarryLookaHead/Index.htm

Your welcome
Jeppe

 

[jeppe]

Ok try this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logic_test1 is
    Port ( A : in  std_logic_vector(5 downto 0);
           Y : out std_logic_vector(5 downto 0));
end logic_test1;

architecture Behavioral of logic_test1 is

begin
   process( A)
	   variable i,j: integer;
   begin
	   Y <= (others => '0'); 
	   i := 1;
		j := 0;
	   while i < 2**5 loop
		 	if A(j)='1' then
			   Y <= Conv_std_logic_vector(i,6);
				exit;
         end if;
			i := i * 2;
			j := j + 1;
		end loop; 
	end process;

end Behavioral;

 

[Govinda]

Thanks a lot Jeppe