Ripple Clock : Quartus 4.1

[Patrick]

Hi everybody,

I have a little problem with the synthesis of this process under Quartus...
Quartus say that this clock (clk_baud) may have ripple...
Perhaps it's due to the Not function ?

It's just a divide per 2 from the "clk_gene" clock

GEN_CLOCK_BAUD : process (clk_gene,init)
begin
if init = '1' then
ck_baud <= '0';
elsif (clk_gene'event and clk_gene='1') then
ck_baud <= not ck_baud;
end if;
end process GEN_CLOCK_BAUD;
clk_baud <= ck_baud;

 

[MikeTreseler]

Quartus say that this clock (clk_baud) may have ripple...

Looks OK to me if
clk_baud is an entity out port,
clk_gene is your system clock, and
ck_baud is an architecture signal.

But consider the version proposed below.

_______________
architecture proposed of divby2 is
begin
GEN_CLOCK_BAUD : process (clk_gene, init) is
variable clk_baud_v : std_ulogic;
begin
if init = '1' then
clk_baud_v := '0';
elsif rising_edge(clk_gene) then
clk_baud_v := not clk_baud_v;
end if;
clk_baud <= clk_baud_v;
end process GEN_CLOCK_BAUD;
end architecture proposed;
-- Mike Treseler