RISC model

  • Thread starter =?ISO-8859-1?Q?Joaqu=EDn_Gracia?=
  • Start date
?

=?ISO-8859-1?Q?Joaqu=EDn_Gracia?=

Hello all,

I'm loking for a VHDL model of a RSIC microcontroller. I have downloaded
a model from www.opencores.org, but it is behavioural. I'm triying to
find a structural (or something behavioural with structural parts) model.

Can someone help me?


Thank you very much, my best regards.
 
M

Mike Treseler

Joaquín Gracia said:
I'm loking for a VHDL model of a RSIC microcontroller. I have downloaded
a model from www.opencores.org, but it is behavioural. I'm triying to
find a structural (or something behavioural with structural parts) model.

What would you do if you had such a model?

-- Mike Treseler
 
T

Thomas Stanka

Hi,

Joaquín Gracia said:
I'm loking for a VHDL model of a RSIC microcontroller. I have downloaded
a model from www.opencores.org, but it is behavioural. I'm triying to
find a structural (or something behavioural with structural parts) model.

What about the Leon processor? (www.gaisler.com)
Its a free Sparc compliant processor core.

bye Thomas
 
H

Hans

I would suggested you do a search for one of the many PIC16C54
implementations available on the internet,

Hans.
www.ht-lab.com



| Hello all,
|
| I'm loking for a VHDL model of a RSIC microcontroller. I have downloaded
| a model from www.opencores.org, but it is behavioural. I'm triying to
| find a structural (or something behavioural with structural parts) model.
|
| Can someone help me?
|
|
| Thank you very much, my best regards.
 
?

=?ISO-8859-1?Q?Joaqu=EDn_Gracia?=

Mike Treseler escribió:
What would you do if you had such a model?

-- Mike Treseler

My intention is to study how a fault can be propagated from
combinational logic to registers, and how this fault can affect the
behaviour of the microcontroller and the workload results.

We have written two papers about this issue, working with a version of
the PIC and another one of the 8051, and we would like to try with
different models.

Joaquin
 

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