rising edge of the clock and data

Discussion in 'VHDL' started by john, Mar 25, 2008.

  1. john

    john Guest

    Hello,

    I am trying to get the following timing waveform

    http://img337.imageshack.us/my.php?image=timingwaveformla7.png


    The timing waveform suggests that data should get ready atleast a half
    cycle before the rising edge of the DCLK. I am unable to do it. My
    program gets the data ready exactly at the rising edge of the clock. I
    know that I can not delay the data. Please advice!

    Regards,
    John
     
    john, Mar 25, 2008
    #1
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  2. john wrote:
    > I am trying to get the following timing waveform
    > http://img337.imageshack.us/my.php?image=timingwaveformla7.png
    > The timing waveform suggests that data should get ready atleast a half
    > cycle before the rising edge of the DCLK. I am unable to do it. My
    > program gets the data ready exactly at the rising edge of the clock. I
    > know that I can not delay the data. Please advice!


    Is that your input or your output timing? If it's your input timing, then I
    would assume you are to generate that signal from your testbench, in which case
    you can use all the delay elements you want. What kind of clock is that DCLK
    anyway or is that just an incorrectly drawn interruption in the clock cycle?

    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Mar 25, 2008
    #2
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  3. john

    john Guest

    Hello,
    Its the output waveform. DCLK is a 50 percent duty cycle 1MHz clock.

    Regards,
    John
     
    john, Mar 25, 2008
    #3
  4. "john" <> wrote in message
    news:...
    >
    > Hello,
    > Its the output waveform. DCLK is a 50 percent duty cycle 1MHz clock.
    >
    > Regards,
    > John
    >


    Are you generating both DCLK and Data as outputs? If so, they hopefully your
    internal clock is running faster than 1MHz. Assuming it is, you just need to
    design your logic that generates the signals to ensure that Data changes
    before DCLK. I would be surprised if you really need half a cycle (500 ns)
    setup time. All you need to ensure is that you meet the documented setup and
    hold times for the device being driven.
     
    David Spencer, Mar 25, 2008
    #4
  5. john wrote:
    > Its the output waveform. DCLK is a 50 percent duty cycle 1MHz clock.


    If your output is both clock and data, consider inverting the clock output.
    Alternatively, use a negative edge clocked FF at the output with a postive edge
    clocked FF right before it (so you have a FF to FF transfer without logic in
    between; should work fine at half clock cycle).

    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Mar 25, 2008
    #5
  6. john

    john Guest

    Hi,
    Can you provide me with RTL view of the logic that you adviced? It
    will be easy for me to follow.
    Thanks
    John
     
    john, Mar 25, 2008
    #6
  7. john

    john Guest

    On Mar 25, 11:02 am, Pieter Hulshoff <> wrote:
    > john wrote:
    > > Its the output waveform. DCLK is a 50 percent duty cycle 1MHz clock.

    >
    > If your output is both clock and data, consider inverting the clock output..
    > Alternatively, use a negative edge clocked FF at the output with a postive edge
    > clocked FF right before it (so you have a FF to FF transfer without logic in
    > between; should work fine at half clock cycle).
    >
    > Kind regards,
    >
    > Pieter Hulshoff


    Hi,

    Should I add the positive edge FF before the negative edge clock for
    CLOCK output or the data output?

    John
     
    john, Mar 25, 2008
    #7
  8. john wrote:
    > Hi,
    > Can you provide me with RTL view of the logic that you adviced? It
    > will be easy for me to follow.
    > Thanks
    > John


    Sure:


    clock inversion solution:

    clk_out <= NOT( dclk );


    FF solution:

    pre_ff_reg: PROCESS IS
    BEGIN
    WAIT UNTIL clk = '1';
    dout_pre <= data_internal;
    END PROCESS pre_ff_reg;

    output_ff_reg: PROCESS IS
    BEGIN
    WAIT UNTIL clk = '0';
    dout <= dout_pre;
    END PROCESS output_ff_reg;

    Add reset code depending on your wants and needs.


    Kind regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Mar 25, 2008
    #8
  9. john

    john Guest

    Hi,

    I tried your advice. Please go to the following link to see the output
    waveform,

    http://img142.imageshack.us/my.php?image=waveformza5.png


    As you can see from the waveform, that everything is happening
    according to plan except one "DCLK" cycle is apperaing just after the
    Tag. The Data is getting stable before the rising edge of the DCLK.
    The Tag looks OK too. But I need to get rid of this one clock cycle
    because it might serial out the zero first and the whole number will
    be wrong. Any advice!

    Regards,
    John
     
    john, Mar 27, 2008
    #9
  10. john

    john Guest

    Hello,

    Your advice did solve the data problem but the "Tag" signal is not
    synchronized at all. I need the "DCLK" to be OFF (zero) when "Tag" is
    high for one clock cycle then "Data" (SER_OUT) has to be at the output
    for half of the "DCLK" clock cycle before the "DCLK" gets to the
    output pin of the FPGA. I got this waveform as you can see in the
    following figure 1

    http://img100.imageshack.us/my.php?image=waveformfq8.png

    I got figure 1 using the state mode of the logic analyzer. But when I
    use the timing mode I get everything same except the Tag repeats
    itself several time during serial outing the one set of data which is
    wrong. Please advice! My code is following

    serialcount : process ( clk_b, Reset_counter)
    begin
    if ( Reset_counter = '1') Then
    p2s_counter <= ( others =>'0');

    elsif rising_edge (clk_b) then
    p2s_counter <= p2s_counter + 1;
    ser_out_sig_1<= ser_buff ( to_integer ( p2s_counter ) );
    else
    end if;
    end process;

    -- Data Clock Delay
    serial_count_delay : process (clk_b, Reset_counter)
    Begin
    if ( Reset_counter = '1') then
    elsif rising_edge(clk_b) then
    ser_out_sig_2 <= ser_out_sig_1;
    else
    end if;
    End process;

    -- Data Clock Second Delay
    process (clk_b, Reset_counter)
    Begin
    if ( Reset_counter = '1') then
    elsif falling_edge(clk_b) then
    ser_out <= ser_out_sig_2;
    else
    end if;
    End process;


    div : process ( clk1x)
    begin
    If ( Reset_counter = '1') Then
    clk_divider <= "00000000000";
    elsIf rising_edge (clk1x) then
    clk_divider <= clk_divider + 1;
    end if;
    end process;

    process(Reset_counter)
    begin
    If ( Reset_counter = '1') Then
    Tag_out_0 <= '1';
    Tag_out_1 <= '1';
    elsif falling_edge (clk_b) then
    Tag_out_1 <= Tag_out_0;
    Tag_out_0 <= '0';
    end if;
    Tag <= Tag_out_1;
    end process;

    Regards,
    John
     
    john, Apr 2, 2008
    #10
  11. john

    jens Guest

    Some random pieces of advice:

    1. Simulate the design.

    2. Use only one clock domain. Synchronize all signals with that
    clock.

    3. Simulate the design.

    4. Where is Reset_counter coming from? If it's coming from the clock
    domain, don't use it as an asynchronous signal. If it isn't coming
    from the clock domain, change it so it is.

    5. Simulate the design.

    6. Look at the logic analyzer's documentation about state vs. timing
    mode (hint: use timing mode for timing analysis). Then only use the
    logic analyzer once you're happy with the simulation results.

    7. Check your sensitivity lists, some are not complete.

    8. Simulate the design.

    9. Format the code using indentation so that it's legible.

    10. Simulate the design.
     
    jens, Apr 2, 2008
    #11
  12. john

    john Guest

    The Reset_counter is generated by the state machine running at much
    higher frequency than the clk_b. How can I make them synchronous?
    John
     
    john, Apr 2, 2008
    #12
  13. john

    jens Guest

    Divide down the high frequency clock to generate a low frequency clock
    enable. Use the high frequency clock as the clock for the entire
    design (if possible). Use the high frequency clock enabled by the low
    frequency clock enable to do everything you need to do at the low
    frequency, something like this:

    if rising_edge(high_freq_clk) then
    if low_freq_clk_en = '1' then
    -- do stuff here
    -- Reset_counter can be used here and will be synchronous
    end if;
    end if;
     
    jens, Apr 3, 2008
    #13
  14. jens wrote:
    > Divide down the high frequency clock to generate a low frequency clock
    > enable. Use the high frequency clock as the clock for the entire
    > design (if possible). Use the high frequency clock enabled by the low
    > frequency clock enable to do everything you need to do at the low
    > frequency, something like this:
    >
    > if rising_edge(high_freq_clk) then
    > if low_freq_clk_en = '1' then
    > -- do stuff here
    > -- Reset_counter can be used here and will be synchronous
    > end if;
    > end if;
     
    Daniel Reidal, Apr 8, 2008
    #14
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