Rising edge of the clock

Discussion in 'VHDL' started by john, Nov 25, 2004.

  1. john

    john Guest

    Hello,


    The problem is that the "Q(0)" bit of the counter is not incrementing
    at the rising edge of the "inc" signal instead its incrementing when
    "inc" signal goes from high to low. I want to increment Q(0) at rising
    edge of the "clk" and rising edge of the signal "inc".
    Please Advice!!
    Thanks
    john


    The code is given below:

    C0: counter port map (Data_out_bus(13 downto 0),DPR_CLK,inc,eq_signal,Reset_A);

    Process ( State, input_signal )

    Begin

    Case State is


    When E0 =>
    Reset_A <='1';
    inc <='0';
    nextstate <=E1;


    When E1 =>

    Reset_A <='0';
    inc <='1';

    nextstate <=E2;

    When E2 =>
    Reset_A <='0';
    inc <='0';

    nextstate <=E1;


    When others =>
    nextstate <=E0;

    End Case;

    End Process;


    -- ( 14 bit )


    Entity counter is

    Port (

    Qout : out unsigned (13 downto 0);
    CLK : in std_logic;
    P : in std_logic;
    count_equal: out std_logic;
    Reset_c: in std_logic


    );

    End counter;

    Architecture count_arch of counter is

    Signal Q : unsigned (13 downto 0);

    Begin

    count_equal <= Q(0);


    Process (Clk, Reset_c)

    Begin


    If (Reset_c = '1' ) then

    Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
    '0', '0', '0', '0', '0', '0', '0' );


    Elsif ( Clk 'event and Clk='1' ) then

    If (P= '1') then

    Q <= Q + 1;

    Qout <=Q;

    End If;

    End if;

    End process;

    End count_arch ;
    john, Nov 25, 2004
    #1
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  2. john

    Neo Guest

    (john) wrote in message news:<>...
    > Hello,
    >
    >
    > The problem is that the "Q(0)" bit of the counter is not incrementing
    > at the rising edge of the "inc" signal instead its incrementing when
    > "inc" signal goes from high to low. I want to increment Q(0) at rising
    > edge of the "clk" and rising edge of the signal "inc".
    > Please Advice!!
    > Thanks
    > john
    >
    >
    > The code is given below:
    >
    > C0: counter port map (Data_out_bus(13 downto 0),DPR_CLK,inc,eq_signal,Reset_A);
    >
    > Process ( State, input_signal )
    >
    > Begin
    >
    > Case State is
    >
    >
    > When E0 =>
    > Reset_A <='1';
    > inc <='0';
    > nextstate <=E1;
    >
    >
    > When E1 =>
    >
    > Reset_A <='0';
    > inc <='1';
    >
    > nextstate <=E2;
    >
    > When E2 =>
    > Reset_A <='0';
    > inc <='0';
    >
    > nextstate <=E1;
    >
    >
    > When others =>
    > nextstate <=E0;
    >
    > End Case;
    >
    > End Process;
    >
    >
    > -- ( 14 bit )
    >
    >
    > Entity counter is
    >
    > Port (
    >
    > Qout : out unsigned (13 downto 0);
    > CLK : in std_logic;
    > P : in std_logic;
    > count_equal: out std_logic;
    > Reset_c: in std_logic
    >
    >
    > );
    >
    > End counter;
    >
    > Architecture count_arch of counter is
    >
    > Signal Q : unsigned (13 downto 0);
    >
    > Begin
    >
    > count_equal <= Q(0);
    >
    >
    > Process (Clk, Reset_c)
    >
    > Begin
    >
    >
    > If (Reset_c = '1' ) then
    >
    > Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
    > '0', '0', '0', '0', '0', '0', '0' );
    >
    >
    > Elsif ( Clk 'event and Clk='1' ) then
    >
    > If (P= '1') then
    >
    > Q <= Q + 1;
    >
    > Qout <=Q;
    >
    > End If;
    >
    > End if;
    >
    > End process;
    >
    > End count_arch ;


    John,
    here you have single register pipeline which is introducing a clock
    delay. you are reading incr which is generated w.r.t to clock in
    another clocked process which is causing the delay. directly run you
    counter in the states to avoid this delay.

    -Neo
    Neo, Nov 26, 2004
    #2
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  3. (john) wrote:
    > The problem is that the "Q(0)" bit of the counter is not incrementing
    > at the rising edge of the "inc" signal instead its incrementing when
    > "inc" signal goes from high to low. I want to increment Q(0) at rising
    > edge of the "clk" and rising edge of the signal "inc".


    I can't see your intention in the code below. To detect rising edges
    synchron you use a shift register.

    test_sr<=test_sr(0)&test_sig
    test_edge<=test_sr(0) and not test_sr(1)

    The problem with your code is, that your counter increments, at the
    next rising edge of clk while inc=1. If inc changes with your clock
    for one clock cycle (can't see in your code, when inc will change in
    relation to CLK) you will see that Q changes with inc but delayed for
    one cycle. A good example why it could be better to use a small
    gatedelay (after 1 ns), to see signals changing delayed to clock.

    > Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
    > '0', '0', '0', '0', '0', '0', '0' );


    Q<=(others=>'0') seems more readable to me and has the same semantics.
    Thomas Stanka, Nov 26, 2004
    #3
  4. john wrote :

    > "inc" signal goes from high to low. I want to increment Q(0) at

    rising
    > edge of the "clk" and rising edge of the signal "inc".
    > Please Advice!!



    I did'nt understand why do you want to check 2 rising edge .It is
    highly impractical .... According to me P is used as Enbale signal
    for the counter....

    If you intend to do then use nested rising edge if statements as
    follows..
    if(clk=1 and clk'Event)then
    if(p=1 and p'Event)then
    Q <=Q+1 ;
    end if ;
    end if ;

    There are many more things to note ...

    > Qout <=Q;

    Qout is inside the Clocked process so Output is one clock cycle
    delayed.

    Check the use of OTHERS keyword and try to use it for assinging long
    words.. like in

    > If (Reset_c = '1' ) then
    >
    > Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
    > '0', '0', '0', '0', '0', '0', '0' );
    >
    >




    Code for the state Machine is not clear and complete But it looks
    like you are reseting the Conter after every increment...
    Mohammed khader, Nov 26, 2004
    #4
  5. john

    john Guest

    Hi Neo,

    The state machine and the counter has the same clock. So, If two
    processes have same clock then still they have delay between them.
    Plus would u please explain that how am I using the single register
    pipeline.
    Please Advice!

    Thanks
    John
    (Neo) wrote in message news:<>...
    > (john) wrote in message news:<>...
    > > Hello,
    > >
    > >
    > > The problem is that the "Q(0)" bit of the counter is not incrementing
    > > at the rising edge of the "inc" signal instead its incrementing when
    > > "inc" signal goes from high to low. I want to increment Q(0) at rising
    > > edge of the "clk" and rising edge of the signal "inc".
    > > Please Advice!!
    > > Thanks
    > > john
    > >
    > >
    > > The code is given below:
    > >
    > > C0: counter port map (Data_out_bus(13 downto 0),DPR_CLK,inc,eq_signal,Reset_A);
    > >
    > > Process ( State, input_signal )
    > >
    > > Begin
    > >
    > > Case State is
    > >
    > >
    > > When E0 =>
    > > Reset_A <='1';
    > > inc <='0';
    > > nextstate <=E1;
    > >
    > >
    > > When E1 =>
    > >
    > > Reset_A <='0';
    > > inc <='1';
    > >
    > > nextstate <=E2;
    > >
    > > When E2 =>
    > > Reset_A <='0';
    > > inc <='0';
    > >
    > > nextstate <=E1;
    > >
    > >
    > > When others =>
    > > nextstate <=E0;
    > >
    > > End Case;
    > >
    > > End Process;
    > >
    > >
    > > -- ( 14 bit )
    > >
    > >
    > > Entity counter is
    > >
    > > Port (
    > >
    > > Qout : out unsigned (13 downto 0);
    > > CLK : in std_logic;
    > > P : in std_logic;
    > > count_equal: out std_logic;
    > > Reset_c: in std_logic
    > >
    > >
    > > );
    > >
    > > End counter;
    > >
    > > Architecture count_arch of counter is
    > >
    > > Signal Q : unsigned (13 downto 0);
    > >
    > > Begin
    > >
    > > count_equal <= Q(0);
    > >
    > >
    > > Process (Clk, Reset_c)
    > >
    > > Begin
    > >
    > >
    > > If (Reset_c = '1' ) then
    > >
    > > Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
    > > '0', '0', '0', '0', '0', '0', '0' );
    > >
    > >
    > > Elsif ( Clk 'event and Clk='1' ) then
    > >
    > > If (P= '1') then
    > >
    > > Q <= Q + 1;
    > >
    > > Qout <=Q;
    > >
    > > End If;
    > >
    > > End if;
    > >
    > > End process;
    > >
    > > End count_arch ;

    >
    > John,
    > here you have single register pipeline which is introducing a clock
    > delay. you are reading incr which is generated w.r.t to clock in
    > another clocked process which is causing the delay. directly run you
    > counter in the states to avoid this delay.
    >
    > -Neo
    john, Nov 27, 2004
    #5
  6. john

    rickman Guest

    john wrote:
    >
    > Hi Neo,
    >
    > The state machine and the counter has the same clock. So, If two
    > processes have same clock then still they have delay between them.
    > Plus would u please explain that how am I using the single register
    > pipeline.
    > Please Advice!
    >
    > Thanks
    > John
    > (Neo) wrote in message news:<>...
    > > (john) wrote in message news:<>...
    > > > Elsif ( Clk 'event and Clk='1' ) then
    > > > If (P= '1') then
    > > > Q <= Q + 1;
    > > > Qout <=Q;
    > > > End If;


    Here you have a register to clock in all the data bits, but the output
    is delayed by another clock cycle to transfer it to the Qout register.
    So the output changes two enabled clocks after the data is input. What
    exactly are you trying to do?

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
    rickman, Nov 28, 2004
    #6
  7. (Mohammed khader) wrote:
    > If you intend to do then use nested rising edge if statements as
    > follows..
    > if(clk=1 and clk'Event)then
    > if(p=1 and p'Event)then
    > Q <=Q+1 ;
    > end if ;
    > end if ;


    I don't believe, that this piece of code will synthesis correctly.
    Never use two clocks in one process for synthesisable code.

    bye Thomas
    Thomas Stanka, Nov 28, 2004
    #7
  8. (Thomas Stanka) wrote in message news:<>...
    > (Mohammed khader) wrote:
    > > If you intend to do then use nested rising edge if statements as
    > > follows..
    > > if(clk=1 and clk'Event)then
    > > if(p=1 and p'Event)then
    > > Q <=Q+1 ;
    > > end if ;
    > > end if ;

    >
    > I don't believe, that this piece of code will synthesis correctly.
    > Never use two clocks in one process for synthesisable code.



    Hi Thomsa,

    I did'nt say that " code will synthesis correctly". I said it is
    hight impractical for this . If any one wants to just simulate then
    will .
    Mohammed khader, Nov 29, 2004
    #8
  9. john wrote:

    > The problem is that the "Q(0)" bit of the counter is not incrementing
    > at the rising edge of the "inc" signal instead its incrementing when
    > "inc" signal goes from high to low. I want to increment Q(0) at rising
    > edge of the "clk" and rising edge of the signal "inc".
    > Please Advice!!


    Ok, here's a few examples:

    1. Assumption: inc is generated on the same clock as the counter process:

    PROCESS
    BEGIN
    WAIT UNTIL clk = '1';
    inc_d <= inc;
    IF inc = '1' AND inc_d = '0' THEN
    Q <= Q + 1;
    END IF;
    Qout <= Q;
    IF reset = '1' THEN
    Q <= (OTHERS => '0');
    Q_out <= (OTHERS => '0');
    inc_d <= '0';
    END IF;
    END PROCESS;

    2. Assumption: inc is generated on another clock as the counter process:

    PROCESS
    BEGIN
    WAIT UNTIL clk = '1';
    inc_c2c <= inc;
    inc_meta <= inc_c2c;
    inc_d <= inc_meta;
    IF inc_meta = '1' AND inc_d = '0' THEN
    Q <= Q + 1;
    END IF;
    Qout <= Q;
    IF reset = '1' THEN
    Q <= (OTHERS => '0');
    Qout <= (OTHERS => '0');
    inc_c2c <= '0';
    inc_meta <= '0';
    inc_d <= '0';
    END IF;
    END PROCESS;

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Nov 29, 2004
    #9
  10. john

    Wong Guest

    (Thomas Stanka) wrote in message news:<>...
    > (Mohammed khader) wrote:
    > > If you intend to do then use nested rising edge if statements as
    > > follows..
    > > if(clk=1 and clk'Event)then
    > > if(p=1 and p'Event)then
    > > Q <=Q+1 ;
    > > end if ;
    > > end if ;

    >
    > I don't believe, that this piece of code will synthesis correctly.
    > Never use two clocks in one process for synthesisable code.
    >
    > bye Thomas


    Yes, I am totally agree. I don't think this is going to work since you
    are detecting both rising edge at the same time exactly.
    Wong, Nov 29, 2004
    #10
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