Rising, falling edge

Discussion in 'VHDL' started by ALuPin, Apr 21, 2005.

  1. ALuPin

    ALuPin Guest

    Hi everybody,

    in the Lattice EC/ECP-handbook there is shown on page 61
    tCK2Q_PFU (Clock to Q delay, D-type register configuration)=0.43ns

    Is that the Clock-To-Output time of an internal FPGA register (not IOs)?


    Do arise any problems with tCO of the first stage when trying the following:

    process(Clk)
    begin
    if rising_edge(Clk) then
    l_sample1 <= Data;
    end if;
    end process;

    process(Clk)
    begin
    if falling_edge(Clk) then
    l_sample2 <= l_sample1;
    end if;
    end if;

    Is there a problem with tCO of l_sample1 that is "l_sample2" samples "l_sample1"
    although "l_sample1" has not changed yet ? (TClk=7,5ns)


    Rgds
    André
     
    ALuPin, Apr 21, 2005
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Anon Anon
    Replies:
    2
    Views:
    1,354
  2. Lore Leunoeg

    assign value on falling edge

    Lore Leunoeg, Jan 27, 2008, in forum: VHDL
    Replies:
    2
    Views:
    578
  3. picnanard
    Replies:
    0
    Views:
    592
    picnanard
    Sep 1, 2008
  4. denish
    Replies:
    5
    Views:
    5,654
  5. Techhead

    Rising Falling Arrow

    Techhead, Mar 28, 2007, in forum: Javascript
    Replies:
    3
    Views:
    142
    Evertjan.
    Mar 28, 2007
Loading...

Share This Page