Rom implementation

Discussion in 'VHDL' started by etoktas, Jul 24, 2006.

  1. etoktas

    etoktas

    Joined:
    Jul 12, 2006
    Messages:
    3
    I have a 256x8 bit look up table in my vhdl design and I reach this look up table 64 times.

    I am using Synplify 8.6.1 for synthesis and tool infers lots of ROMs for this table.As far as I understand this inferred ROMs are made up of logic gates not reserved block RAMs in the technology resources.


    I heard that there is an attribute for Xilinx Virtex family named "select_ROM"
    in order to use RAM blocks to implement these ROMs without wasting combinatorial blocks .

    Is there such an attribute for Actel family?"


    I would appreciate your help.
    etoktas, Jul 24, 2006
    #1
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