RS232 help!

[power_hf2005]

I'm in problem with RS232, my idea is very simple. I just design a receiver( no transmitter). My purpose is to control LEDs in my KIT, ex: when I type "a", these LEDs will be "0011", and "r" with "1100". But I fail! Can you help me to solve this problem?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity vao is
GENERIC (baud : integer := 9600; f_clock : integer := 50000000);
port(
RS232_in : in std_logic;
clock : in std_logic;
LED: out std_logic_vector(3 downto 0)
);
end vao;

architecture vao of vao is
signal data : std_logic_vector(7 downto 0);
signal t_count : std_logic_vector(19 downto 0);

signal rx : std_logic;

signal reg : std_logic_vector(9 downto 0);
signal b_count : std_logic_vector(3 downto 0);

TYPE STATE_TYPE IS (idle, s_start, s_wait, s_get, s_done);
SIGNAL ss : STATE_TYPE;
CONSTANT a: std_logic_vector( 7 downto 0):=X"61";
CONSTANT r: std_logic_vector(7 downto 0):=X"72";
CONSTANT full_tick : integer := f_clock/baud;
CONSTANT half_tick : integer := full_tick/2;

begin

PROCESS (clock)
BEGIN
IF clock'EVENT AND clock = '1' THEN
rx <= RS232_in;
CASE ss IS
WHEN idle =>
t_count <= X"00000";
IF rx = '0' THEN ss <= s_start; END IF;
WHEN s_start =>
b_count <= X"0";
t_count <= t_count+1;
if t_count=half_tick then ss <= s_get; end if;
WHEN s_wait =>
t_count <= t_count+1;
if t_count=full_tick then ss <= s_get; end if;
WHEN s_get =>
t_count <= X"00000";
b_count <= b_count+1;
reg <= rx & reg(9 downto 1) ;
IF b_count=X"A" THEN
ss <= s_done;
ELSE
ss <= s_wait;
END IF;
WHEN s_done =>
data <= reg(7 downto 0);
ss <= idle;
END CASE;
END IF;
if data=a then
LED<="0011";
elsif data= r then
LED<="1100";
end if;
end process;
end vao;

 

[jeppe]

Understand how signals handled in VHDL

Hi

Hopefully will this revision of your code work alright (not simulated)

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vao is
      GENERIC (baud : integer := 9600; f_clock : integer := 50000000);
      port( RS232_in : in std_logic;
            clock : in std_logic;
            LED: out std_logic_vector(3 downto 0));
end vao;

architecture vao of vao is
   signal data : std_logic_vector(7 downto 0);
   signal t_count : std_logic_vector(19 downto 0);
   signal rx : std_logic;
   signal reg : std_logic_vector(9 downto 0);
   signal b_count : std_logic_vector(3 downto 0);

   TYPE STATE_TYPE IS (idle, s_start, s_wait, s_get, s_done);
   SIGNAL ss : STATE_TYPE;
   CONSTANT a: std_logic_vector( 7 downto 0):=X"61";
   CONSTANT r: std_logic_vector(7 downto 0):=X"72";
   CONSTANT full_tick : integer := f_clock/baud;
   CONSTANT half_tick : integer := full_tick/2;
begin
   --Please note - if a signal give a value twice within a
   -- process will it ONLY get the last value given.
   -- Search the net for EVITA VHDL from ALDEC.COM 
   -- Watch chapter 6 of the interactive book on VHDL and
   -- understand how signal handled in VHDL.

   PROCESS (clock,data)
   BEGIN
      IF clock'EVENT AND clock = '1' THEN
         rx <= RS232_in;
         CASE ss IS
            WHEN idle =>
               t_count <= X"00000";
               IF rx = '0' THEN 
                  ss <= s_start; 
                  b_count <= X"0";
               END IF;
            WHEN s_start =>               
               t_count <= t_count+1;
               if t_count=half_tick then 
                  ss      <= s_get; 
                  t_count <= X"00000";               
               end if;
            WHEN s_wait =>
               t_count <= t_count+1;
               if t_count=full_tick then 
                  t_count <= X"00000"; 
                  ss <= s_get; 
               end if;
            WHEN s_get =>
               b_count <= b_count+1;
               reg <= rx & reg(9 downto 1) ;
               IF b_count=X"A" THEN 
                  ss <= s_done; 
               ELSE
                  ss <= s_wait;
               END IF;
            WHEN s_done =>
               data <= reg(7 downto 0);
               ss <= idle;
         END CASE;
      END IF;
      if data=a then
         LED<="0011";
      elsif data= r then
         LED<="1100";
      end if;
   end process;
end vao;

Jeppe

 

[power_hf2005]

can u tell me what should I know and prepare to design a receiver? I mean that some knowledge about VHDL, hardware . For ex, how "case", "if" .... in VHDL work or how a register, counter work...etc... I ask that because I'm studying VHDL by myself at home with my kIT. I think my study is in wrong way:-(

 

[jeppe]

In the case "RS232 Reciever" seems your design to be ok - if you search textbook will you normally be adviced to use a scan_frequency x16 higher then the Baud frequency - but your way of detecting the start_bit even better.

In the matter VHDL could you visit http://web.sdu.dk/jjm/MMMI/VHDL/Kompendie/Mux/case_is.htm
or
http://jjmk.dk/MMMI/VHDL/Kompendie/Sekventiel/case_is_when.htm