RS232 problem with post-routing simulation

Discussion in 'VHDL' started by Gekko, Oct 6, 2007.

  1. Gekko

    Gekko

    Joined:
    Oct 6, 2007
    Messages:
    3
    Hi,

    I'm a newbie in VHDL and i'm trying to get a RS232 connection working with my XUP virtex-II Pro FPGA board.

    I used the following code below (which i made myself based with help of internet (FPGA4fun)) and it works fine in the behaverioul simulation. But when i try the post-route simulation, i do not get the results i wanted. I don't know how to check whats going wrong. Prolly timing issues or obvious things i don't know cuz lack of experience. I used clock high = 15 ns = clock low, input setup time = 1 ns = output valid delay. The generation of the baud_ticks works fine. I think it's the case-thingie that forms problems

    ------------------------------------------------------------
    entity Main is
    Port ( clk_fpga : in STD_LOGIC;
    TxD : out STD_LOGIC := '1';
    TxD_busy : out STD_LOGIC;
    baud_tick_out : out STD_LOGIC);
    end Main;


    architecture Behavioral of Main is
    signal baud_tick : STD_LOGIC;
    signal nextstate : integer := 0;
    signal busy : STD_LOGIC := '0';

    signal TxD_data : STD_LOGIC_VECTOR(7 downto 0) := "10010101";
    signal TxD_start : STD_LOGIC := '1';


    COMPONENT Baud_generator_asyn
    Port( clk : in std_logic;
    enable : in std_logic;
    baud_tick : out std_logic);
    END COMPONENT;


    begin

    baud_gen_asyn: Baud_generator_asyn PORT MAP(
    clk => clk_fpga,
    enable => '1',
    baud_tick => baud_tick
    );


    process(Txd_start,baud_tick,TxD_data)
    begin
    case nextstate is
    when 0 => if TxD_start = '1' then nextstate <= 1; busy <= '1'; end if;
    when 1 => if baud_tick = '1' then nextstate <= 2; TxD <= '0'; end if; --start
    when 2 => if baud_tick = '1' then nextstate <= 3; TxD <= TxD_data(0); end if; --bit0
    when 3 => if baud_tick = '1' then nextstate <= 4; TxD <= TxD_data(1); end if; --bit1
    when 4 => if baud_tick = '1' then nextstate <= 5; TxD <= TxD_data(2); end if; --bit2
    when 5 => if baud_tick = '1' then nextstate <= 6; TxD <= TxD_data(3); end if; --bit3
    when 6 => if baud_tick = '1' then nextstate <= 7; TxD <= TxD_data(4); end if; --bit4
    when 7 => if baud_tick = '1' then nextstate <= 8; TxD <= TxD_data(5); end if; --bit5
    when 8 => if baud_tick = '1' then nextstate <= 9; TxD <= TxD_data(6); end if; --bit6
    when 9 => if baud_tick = '1' then nextstate <= 10; TxD <= TxD_data(7); end if; --bit7
    when 10 => if baud_tick = '1' then nextstate <= 11; TxD <= '1'; end if; --stopbit1
    when 11 => if baud_tick = '1' then nextstate <= 12; TxD <= '1'; end if; --busy <= '0'; end if; --stopbit2
    when 12 => if baud_tick = '1' then nextstate <= 0; busy <= '0'; end if;
    when others => if baud_tick = '1' then nextstate <= 0; TxD <= '1'; end if;
    end case;
    end process;

    process(busy)
    begin
    TxD_busy <= busy after 5 ns;
    end process;

    process(baud_tick)
    begin
    baud_tick_out <= baud_tick after 5 ns;
    end process;

    end Behavioral;

    --------------------------------------------
    entity Baud_generator_asyn is
    Port ( clk : in STD_LOGIC; --CLOCK MUST BE 32 MHZ
    enable : in STD_LOGIC := '0';
    baud_tick : out STD_LOGIC
    );
    end Baud_generator_asyn;

    architecture Behavioral of Baud_generator_asyn is

    begin

    process(clk,enable)
    variable baud_acc : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
    begin
    if rising_edge(clk) then
    if enable = '1' then
    baud_acc := ("0" & baud_acc(14 downto 0)) + ( "0000000001110110");
    else
    baud_acc := "0000000000000000";
    end if;
    end if;
    baud_tick <= baud_acc(15);
    end process;

    end Behavioral;
    ----------------------------------------

    If you want me to show simulation pictures or something. You can always ask :D. I've looked in a lot of VHDL tutorials and that is a popular way to do sequential code. But it just doenst work beyond behaverioul simulation :S

    Thx in advance
     
    Last edited: Oct 6, 2007
    Gekko, Oct 6, 2007
    #1
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  2. Gekko

    Gekko

    Joined:
    Oct 6, 2007
    Messages:
    3
    I also tried another method with wait commands

    process
    begin
    wait until rising_edge(TxD_start); busy <= '1;
    wait until rising_edge(baud_tick); TxD <= '0'; --start
    wait until rising_edge(baud_tick); TxD <= TxD_data(0); --bit0
    wait until rising_edge(baud_tick); TxD <= TxD_data(1); --bit1
    wait until rising_edge(baud_tick); TxD <= TxD_data(2); --bit2
    wait until rising_edge(baud_tick); TxD <= TxD_data(3); --bit3
    wait until rising_edge(baud_tick); TxD <= TxD_data(4); --bit4
    wait until rising_edge(baud_tick); TxD <= TxD_data(5); --bit5
    wait until rising_edge(baud_tick); TxD <= TxD_data(6); --bit6
    wait until rising_edge(baud_tick); TxD <= TxD_data(7); --bit7
    wait until rising_edge(baud_tick); TxD <= '1'; --stopbit1
    wait until rising_edge(baud_tick); TxD <= '1'; --stopbit2
    wait until rising_edge(clk_fpga); busy <= '0';
    end process;

    But it gives the error that i cant have multiple waits with different conditions. Is that normal? I find it weird that there would be such a restriction.

    -->line 63: Same wait conditions expected in all Multiple Waits.
     
    Gekko, Oct 6, 2007
    #2
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  3. Gekko

    Gekko

    Joined:
    Oct 6, 2007
    Messages:
    3
    Hi again,

    I also tried this piece of code:

    process(baud_tick)
    variable state, nextstate : integer := 0;
    begin
    case state is
    when 0 => if TxD_start = '1' and baud_tick = '1' then nextstate := 1; busy <= '1'; end if;
    when 1 => if baud_tick = '1' then nextstate := 2; TxD <= '0'; end if; --start
    when 2 => if baud_tick = '1' then nextstate := 3; TxD <= TxD_data(0); end if; --bit0
    when 3 => if baud_tick = '1' then nextstate := 4; TxD <= TxD_data(1); end if; --bit1
    when 4 => if baud_tick = '1' then nextstate := 5; TxD <= TxD_data(2); end if; --bit2
    when 5 => if baud_tick = '1' then nextstate := 6; TxD <= TxD_data(3); end if; --bit3
    when 6 => if baud_tick = '1' then nextstate := 7; TxD <= TxD_data(4); end if; --bit4
    when 7 => if baud_tick = '1' then nextstate := 8; TxD <= TxD_data(5); end if; --bit5
    when 8 => if baud_tick = '1' then nextstate := 9; TxD <= TxD_data(6); end if; --bit6
    when 9 => if baud_tick = '1' then nextstate := 10; TxD <= TxD_data(7); end if; --bit7
    when 10 => if baud_tick = '1' then nextstate := 11; TxD <= '1'; end if; --stopbit1
    when 11 => if baud_tick = '1' then nextstate := 12; TxD <= '1'; end if; --busy <= '0'; end if; --stopbit2
    when 12 => if baud_tick = '1' then nextstate := 0; busy <= '0'; end if;
    when others => if baud_tick = '1' then nextstate := 0; TxD <= '0'; end if;
    end case;
    if baud_tick = '0' then
    state := nextstate;
    end if;
    end process;

    Behaverioul works just fine, but post-route not. The odd part is that if I change the part in bold to TxD <= '1'; iI get a DIFFERENT result??? But normally it's not supposed to ever get there, right :dontknow: ? Something wrong with my declarations? I don't understaaaaand, plz help :D
     
    Gekko, Oct 6, 2007
    #3
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