runtime arguments in VHDL (ala plusargs in Verilog)

[Mark]

Got another how do you things like in Verilog in VHDL question:
what's the "best" way to pass runtime arguements to a compiled VHDL
design? Write the test name to a file, and have the tb read the file,
and execute a particular test procedure? I've seen a Modeltech
example where the simulator force command was used to setup variables,
but that seems rather clunky to me.

Thanks,

Mark

 

[Allan Herriman]

Got another how do you things like in Verilog in VHDL question: what's
the "best" way to pass runtime arguements to a compiled VHDL design?
Write the test name to a file, and have the tb read the file, and
execute a particular test procedure? I've seen a Modeltech example
where the simulator force command was used to setup variables, but that
seems rather clunky to me.

If the design has been compiled but not elaborated, the easiest way might
be to pass the arguments in as generics. These can be of any type,
including string and enumerated types.

You can set the generics by using the -g or -G switches in vsim.

It gets a little more complicated if you have a mix of verilog and VHDL
in your hierarchy.

N.B. Not all tools support setting the value of generics of an enumerated
type in this way.

Regards,
Allan

 

[Mike Treseler]

Got another how do you things like in Verilog in VHDL question:
what's the "best" way to pass runtime arguements to a compiled VHDL
design? Write the test name to a file, and have the tb read the file,
and execute a particular test procedure?

That would not be my recommendation.
I use vhdl procedures, and simple vsim -G generics.
See the testbench example here:
http://mysite.verizon.net/miketreseler/

 

[Mark]

That would not be my recommendation.
I use vhdl procedures, and simple vsim -G generics.
See the testbench example here:http://mysite.verizon.net/miketreseler/

Thanks. I'll follow that model.