M
M. Norton
Hello,
After a long period of looking for work, I'm back in the saddle
writing VHDL and quite happy about it. On the downside, there are a
few regions where I am a bit rusty. Addtionally I have some
colleagues who are more novice, some of them writing their first VHDL
for FPGA devices on their boards and I've become sort of a mentor,
alarming though that may be ;-)
Anyhow to the point, I'm looking for some help with simulation and
managing multiple configurations along with any best practices and
recommendations for structure. For example, a colleague has his RTL
code and has performed synthesis and I was trying to demonstrate how
he can run his testbench against the back-annotated VHDL the place and
route tool provided. So in the testbench we had something like:
entity design_tb is
end entity design_tb;
architecture beh of design_tb is
component foo_design
end component foo_design;
begin
DUT : foo_design port map ();
end architecture beh;
We have an RTL description of the design, and then the VHDL that was
generated from the place & route tool, labeled def_arch. I added a
couple of configurations at the end of the testbench file thinking he
could comment and uncomment them as needed for whatever he was trying
to simulate.
configuration back_annotated of design_tb is
for beh
for all : foo_design
use entity work.foo_design(def_arch);
end for;
end for;
end configuration back_annotated;
configuration functional of design_tb is
for beh
for all : foo_design
use entity work.foo_design(rtl);
end for;
end for;
end configuration functional;
However, commenting and uncommenting the desired configuration with a
recompile afterwards did not seem to do the trick, it was always using
the most recently compiled architecture for the design, regardless of
what configuration was active. So it seems to me like I've got
something wrong. And additionally, this was what I came up with on
the spur of the moment. As noted above, I'm all ears for best
practices for creating multiple simulation configurations. It's ALSO
entirely possible there's something special in Modelsim's invocation
of vsim that I'm not specifying correctly. I admit we're using the
GUI heavily due to me still feeling rusty. I felt fortunate that I
still remembered how to invoke an SDF file to use with the
backannotated design, but likewise felt bad I couldn't figure out how
to get it to invoke the correct architecture that makes the SDF file
meaningful.
Any ideas? How do you collective designers manage this issue?
Thanks!
Mark Norton
After a long period of looking for work, I'm back in the saddle
writing VHDL and quite happy about it. On the downside, there are a
few regions where I am a bit rusty. Addtionally I have some
colleagues who are more novice, some of them writing their first VHDL
for FPGA devices on their boards and I've become sort of a mentor,
alarming though that may be ;-)
Anyhow to the point, I'm looking for some help with simulation and
managing multiple configurations along with any best practices and
recommendations for structure. For example, a colleague has his RTL
code and has performed synthesis and I was trying to demonstrate how
he can run his testbench against the back-annotated VHDL the place and
route tool provided. So in the testbench we had something like:
entity design_tb is
end entity design_tb;
architecture beh of design_tb is
component foo_design
end component foo_design;
begin
DUT : foo_design port map ();
end architecture beh;
We have an RTL description of the design, and then the VHDL that was
generated from the place & route tool, labeled def_arch. I added a
couple of configurations at the end of the testbench file thinking he
could comment and uncomment them as needed for whatever he was trying
to simulate.
configuration back_annotated of design_tb is
for beh
for all : foo_design
use entity work.foo_design(def_arch);
end for;
end for;
end configuration back_annotated;
configuration functional of design_tb is
for beh
for all : foo_design
use entity work.foo_design(rtl);
end for;
end for;
end configuration functional;
However, commenting and uncommenting the desired configuration with a
recompile afterwards did not seem to do the trick, it was always using
the most recently compiled architecture for the design, regardless of
what configuration was active. So it seems to me like I've got
something wrong. And additionally, this was what I came up with on
the spur of the moment. As noted above, I'm all ears for best
practices for creating multiple simulation configurations. It's ALSO
entirely possible there's something special in Modelsim's invocation
of vsim that I'm not specifying correctly. I admit we're using the
GUI heavily due to me still feeling rusty. I felt fortunate that I
still remembered how to invoke an SDF file to use with the
backannotated design, but likewise felt bad I couldn't figure out how
to get it to invoke the correct architecture that makes the SDF file
meaningful.
Any ideas? How do you collective designers manage this issue?
Thanks!
Mark Norton