Sample code

[shah_satish2002]

Hi..
I am new and i dont have much knowledge about VHDL..Here is my code.


Library IEEE;
Use IEEE.std_logic_1164.all;

Entity Del is
port( M1,M2,M3,SEL: in bit;
bit1,bit2,bit3: out bit);
End Entity Del;

Architecture FA_calc of Del is

begin


process (SEL,M1,M2,M3)

variable IN_vector: bit_vector(3 downto 0);
begin

loop1: for i in 0 to 11 loop

IN_vector := SEL & M1 & M2 & M3 ;

case IN_vector is

when "0000" => bit1<='0'; bit2 <= '0';bit3 <= '0';
when "0100" => bit1<='0'; bit2 <= '0';bit3 <= '0';

when "1100" => bit1<='1'; bit2 <= '0';bit3 <= '0';
when "1110" => bit1<='1'; bit2 <= '0';bit3 <= '0';

when "0110" => bit1<='1'; bit2 <= '1';bit3 <= '0';

when "0010" => bit1<='1'; bit2 <= '1';bit3 <= '0';

when "1010" => bit1<='0'; bit2 <= '1';bit3 <= '0';

when "1011" => bit1<='0'; bit2 <= '1';bit3 <= '0';

when "0011" => bit1<='0'; bit2 <= '1';bit3 <= '1';

when "0111" => bit1<='0'; bit2 <= '1';bit3 <= '1';

when "1111" => bit1<='1'; bit2 <= '1';bit3 <= '1';

when "1101" => bit1<='1'; bit2 <= '1';bit3 <= '1';

when "0101" => bit1<='1'; bit2 <= '0';bit3 <= '1';

when "0001" => bit1<='1'; bit2 <= '0';bit3 <= '1';

when "1001" => bit1<='0'; bit2 <= '0';bit3 <= '1';

when "1000" => bit1<='0'; bit2 <= '0';bit3 <= '1';

End case;

-- SEL := bit3 ; Here i want to make " bit 3 = SEL "is the input for next cycle.


end loop loop1;
end process;

End Architecture FA_calc ;


Here I need to create Clock.. and my clock frequency is 24 mhz.I need to rotate my cycle 12 times..so i can get 24 bit out put (i need only bit 1 and bit 2 at every cycle as a out put..Bit 3 is the input for next cycle)..But end of the cycle (12th cycle, My out put is bit1,bit2 and bit3)

Please help me out..I know my code is not perfect..

I hope, my question will be clear.