sane input

Discussion in 'VHDL' started by shane, Oct 3, 2008.

  1. shane

    shane Guest

    I'm designing a basic component, and I've realised that the input could be non
    sensible. I have 3 input signals (not including a vector that inputs a value)
    I want to be sure that the 3 input signals can never be actioned at the same
    time (I want to avoid a race condition)
    Could someone point me in the right direction?

    TIA
    --
    Hardware n: Parts of the computer you can kick
    shane, Oct 3, 2008
    #1
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  2. shane

    KJ Guest

    On Oct 3, 1:57 am, shane <-a-geek.net> wrote:
    > I'm designing a basic component, and I've realised that the input could be non
    > sensible.  I have 3 input signals (not including a vector that inputs a value)
    > I want to be sure that the 3 input signals can never be actioned at the same
    > time (I want to avoid a race condition)


    1. You don't control inputs, they control your design.
    2. Simple logic, Bad_Input <= Inp1 and Inp2 and Inp3.
    3. Race condition implies a path somewhere to a storage element but
    you haven't given enough details to go much further.
    4. Comparing the values of each of the inputs to what they were at
    some previous time to see if they are all stable will filter out many
    bogus inputs. How long there should be between 'now' and 'previous
    time' depends on how long you expect that whatever is creating the
    invalid inputs will be doing its thing. Increasing that time
    increases your reliability, but at the same time decreases your
    responsiveness.

    Kevin Jennings
    KJ, Oct 3, 2008
    #2
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  3. shane

    shane Guest

    Jonathan Bromley did scribble:

    > On Fri, 03 Oct 2008 18:57:13 +1300, shane <-a-geek.net>
    > wrote:
    >
    >>I'm designing a basic component, and I've realised that the input could be non
    >>sensible. I have 3 input signals (not including a vector that inputs a value)
    >>I want to be sure that the 3 input signals can never be actioned at the same
    >>time (I want to avoid a race condition)
    >>Could someone point me in the right direction?

    >
    > Only if you can be a bit more specific. What do you mean
    > by "actioned"? Are these three signals all clocks, or are they
    > enable or trigger signals that can be sampled by a single common
    > clock? (I very much hope it's the latter.) More clues needed.


    Hi, yes

    I don't have a clock in my component ( I am very new to this so feel free to
    correct me.. gently :))

    I have three trigger signals incoming, that my component will react to. My
    concern is that I have no control on their timing, so am trying to design a
    sane reaction(?)

    The trigger signals instruct the component to do the following:
    load a value from the vector signal
    increment that value
    write enable, allow the value stored in the component to be read from the
    outside
    --
    Hardware n: Parts of the computer you can kick
    shane, Oct 3, 2008
    #3
  4. shane wrote:

    > I don't have a clock in my component ( I am very new to this so feel free to
    > correct me.. gently :))


    1. Add a clock and use it to synchronize the inputs.
    2. Write a synchronous process to do the loads, stores and increments.
    Some examples:
    http://mysite.verizon.net/miketreseler/

    -- Mike Treseler
    Mike Treseler, Oct 3, 2008
    #4
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