Second argument of write must have a constant value.

Discussion in 'VHDL' started by Nikola Skoric, Jun 14, 2006.

  1. Hello there,

    I'm rather new to VHDL and find this piece of code perfectly legitimate:

    architecture Behavioral of writer is
    file FP: TEXT open write_mode is "output.txt";
    begin
    process (write) is
    variable l : line;
    variable data : std_logic_vector(63 downto 0);
    begin
    if (rising_edge(write)) then
    data := DATA_in;
    write(l,data);
    writeline(FP,l);
    end if;
    end process;

    end Behavioral;

    But my analyzer disagrees, and says: "Second argument of write must have
    a constant value." What should I do to please my analyzer?

    --
    "Now the storm has passed over me
    I'm left to drift on a dead calm sea
    And watch her forever through the cracks in the beams
    Nailed across the doorways of the bedrooms of my dreams"
     
    Nikola Skoric, Jun 14, 2006
    #1
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  2. Nikola Skoric <> writes:

    > I'm rather new to VHDL and find this piece of code perfectly legitimate:

    [...]
    > process (write) is


    I wouldn't reuse that function name for a signal.

    Cheers,
    Colin
     
    Colin Marquardt, Jun 15, 2006
    #2
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  3. Nikola Skoric

    Guest

    I'm guessing that you're using textio:

    write(L, VALUE, JUSTIFY, FIELD); -- Write one value to "line" L from
    variable VALUE
    * Data_type of VALUE can be bit, bit_vector, integer, real,
    character, string, or time.
    * JUSTIFY is "left" or "right" to justify within the field
    * FIELD is the desired field width of the written value


    You must convert the value from std_logic_vector to bit_vector before
    write will accept it.
     
    , Jun 15, 2006
    #3
  4. In article <>,
    says...
    > I'm guessing that you're using textio:
    >
    > write(L, VALUE, JUSTIFY, FIELD); -- Write one value to "line" L from
    > variable VALUE
    > * Data_type of VALUE can be bit, bit_vector, integer, real,
    > character, string, or time.
    > * JUSTIFY is "left" or "right" to justify within the field
    > * FIELD is the desired field width of the written value
    >
    >
    > You must convert the value from std_logic_vector to bit_vector before
    > write will accept it.


    Oh, right. Thanks. Works now.

    While we're at it, can you recommend me some kind of VHDL reference? For
    instance, this code I've written dumps a series of bits to the file...
    and now I'd like to convert that bit_vector to string containing hex
    digits. Where do I start seraching for such a function?

    --
    "Now the storm has passed over me
    I'm left to drift on a dead calm sea
    And watch her forever through the cracks in the beams
    Nailed across the doorways of the bedrooms of my dreams"
     
    Nikola Skoric, Jun 15, 2006
    #4
  5. Colin Marquardt, Jun 15, 2006
    #5
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