Seed Values

Discussion in 'VHDL' started by FPGA, Feb 25, 2008.

  1. FPGA

    FPGA Guest

    I would like to know how the initialisation of seed values would
    affect the output of the procedure of UNIFORM. I have looked at
    UNIFORM but I am not able to understand the significance of the seed
    values.
    I have written a process to generate random signed vectors. In my
    case, i specify that the random number be in range min and max.
    When I change the seed values, I still get the same sequence of random
    numbers. I am not sure if this is how it should behave.
    All I have done is converted the real to signed using rand <=
    toSigned((real(min) + (rand1 * (real(max)-real(min)));
    How do I simulate this process. I am getting random numbers, but I
    would like to write a test bench which would check for all possible
    scenarios and worst cases.
    Thanks in advance
    FPGA, Feb 25, 2008
    #1
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  2. FPGA

    Jim Lewis Guest

    FPGA WITH NO NAME (I prefer to talk to humans),
    > I would like to know how the initialisation of seed values would
    > affect the output of the procedure of UNIFORM. I have looked at
    > UNIFORM but I am not able to understand the significance of the seed
    > values.
    > I have written a process to generate random signed vectors. In my
    > case, i specify that the random number be in range min and max.
    > When I change the seed values, I still get the same sequence of random
    > numbers. I am not sure if this is how it should behave.

    You should be getting a different sequence. Did you do all of your
    process steps (save file, recompile, re-run simulation)?
    Is there a bug in your scaling process?

    Just for fun, write a test program that loops while generating random values.
    How many times does it need to loop before all values are generated?
    After going through your loop n times where n = range of values,
    how many values are not covered? I usually track this in an array.


    > All I have done is converted the real to signed using rand <=
    > toSigned((real(min) + (rand1 * (real(max)-real(min)));

    This looks ok other than toSigned. I use ieee.nummeric_std.to_signed
    I am not sure where toSigned comes from.

    > How do I simulate this process. I am getting random numbers, but I
    > would like to write a test bench which would check for all possible
    > scenarios and worst cases.


    There is the fun stuff. You will have to enumerate what these are and
    write code to track them. For help you will need to be more specific.

    Cheers,
    Jim
    Jim Lewis, Feb 25, 2008
    #2
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  3. FPGA wrote:

    > I would like to know how the initialisation of seed values would
    > affect the output of the procedure of UNIFORM. I have looked at
    > UNIFORM but I am not able to understand the significance of the seed
    > values.


    You initialize the seed values once. After that, they are modified by the
    calls to uniform. You should not change the seed values anymore. Unless you
    want to repeat the generated random values. Because that is what the seed
    value guarantees: initialize them with the same values as before, and
    uniform will generate the exact same numbers as before.


    > I have written a process to generate random signed vectors. In my
    > case, i specify that the random number be in range min and max.
    > When I change the seed values, I still get the same sequence of random
    > numbers.


    Are you sure?

    > I am not sure if this is how it should behave.
    > All I have done is converted the real to signed using rand <=
    > toSigned((real(min) + (rand1 * (real(max)-real(min)));
    > How do I simulate this process. I am getting random numbers, but I
    > would like to write a test bench which would check for all possible
    > scenarios and worst cases.


    Something like:

    use std.textio.all;
    ...
    process is
    variable l: line;
    variable rand : integer; (or signed())
    variable seed1, seed2: integer;
    begin
    seed1 := 123;
    seed2 := 5678;
    for i in 1 to 1000 loop
    rand := your random function, calling uniform()
    write(l, rand);
    writeline(output, l);
    end loop;
    wait;
    end process;

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Feb 25, 2008
    #3
  4. FPGA

    FPGA Guest

    On Feb 25, 11:41 am, Jim Lewis <> wrote:
    > FPGA WITH NO NAME (I prefer to talk to humans),> I would like to know how the initialisation of seed values would
    > > affect the output of the procedure of UNIFORM. I have looked at
    > > UNIFORM but I am not able to understand the significance of the seed
    > > values.
    > > I have written a process to generate random signed vectors. In my
    > > case, i specify that the random number be in range min and max.
    > > When I change the seed values, I still get the same sequence of random
    > > numbers. I am not sure if this is how it should behave.

    >
    > You should be getting a different sequence.  Did you do all of your
    > process steps (save file, recompile, re-run simulation)?
    > Is there a bug in your scaling process?

    I have saved, recompiled and rerun simulation. The strange thing is, I
    am getting the same sequence if I output uniform in real format even
    after I change the initialisation of Seed1 and Seed2.
    uniform(S1,S2,rand1);
    rand_real <= rand1;

    I am not sure why this is happening.
    SEED1 <= 10;--1 ;
    SEED2 <= 20;--2147483647 ;

    >
    > Just for fun, write a test program that loops while generating random values.
    > How many times does it need to loop before all values are generated?
    > After going through your loop n times where n = range of values,
    > how many values are not covered?  I usually track this in an array.
    >
    >  > All I have done is converted the real to signed using rand <=
    >  > toSigned((real(min) + (rand1 * (real(max)-real(min)));
    > This looks ok other than toSigned.  I use ieee.nummeric_std.to_signed
    > I am not sure where toSigned comes from.

    toSigned converts real to signed of specified bw. I dont see any
    problem with toSigned.
    >
    > > How do I simulate this process. I am getting random numbers, but I
    > > would like to write a test bench which would check for all possible
    > > scenarios and worst cases.

    >
    > There is the fun stuff.  You will have to enumerate what these are and
    > write code to track them.  For help you will need to be more specific.


    I am dealing with someone who himself doesnt know what he wants. I
    would just like to write smthg to prove that it works correctly,
    nothing very particular.
    >
    > Cheers,
    > Jim
    FPGA, Feb 25, 2008
    #4
  5. FPGA wrote:

    >> process steps (save file, recompile, re-run simulation)?
    >> Is there a bug in your scaling process?

    > I have saved, recompiled and rerun simulation. The strange thing is, I
    > am getting the same sequence if I output uniform in real format even
    > after I change the initialisation of Seed1 and Seed2.
    > uniform(S1,S2,rand1);
    > rand_real <= rand1;
    >
    > I am not sure why this is happening.
    > SEED1 <= 10;--1 ;
    > SEED2 <= 20;--2147483647 ;


    Use variables for SEED1 and SEED2, or make sure there is a wait after
    assigning the signals.

    Signals are only updated after a delta delay. So if you do:

    SEED1 <= 10;--1 ;
    SEED2 <= 20;--2147483647 ;
    uniform(SEES1,SEED2,rand1);

    then uniform uses the values of SEED1 and SEED2 from *before* the
    assignment.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Feb 26, 2008
    #5
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