Hi RP,
crazyrdx said:
I have read that simulation is much better if there is a clear
separation of control and data paths in VHDL. Can someone give me an
example code of this?
I am not sure about getting "better" simulation results, whatever that
means. To me it's more a matter of coding style (which in turn is
often a matter of the targeted application), similar to the never
ending discussions about the benefits of 1/2/3-process FSMs. Actually,
a 2+-process FSM separates control and data paths as well.
OK, here's my example. Think of a register file with N registers. You
could separate the address decoding logic (control path) from register
assignment (data path). Your address decoder would translate the
address to a more abstract representation.
case addr
[...]
when "0101010" => enable_reg <= 99; -- the binary address doesn't have to
-- correspond with the actual index
[...]
end case;
-- this goes into a clocked process
reg[enable_reg] <= data;
Regards,
Marcus