serial clock generation

Discussion in 'VHDL' started by vu, Aug 21, 2006.

  1. vu

    vu Guest

    Hello,

    I've just very recently started VHDL coding, and still unfamiliar with
    the proper style of the language.

    I am trying to create a serial interface that receives a serial clock
    (seperate from system clock), and inverts this clock to make a transmit
    clock. What would be the best method to do this? I would appreciate a
    snippet of code if possible.

    Thank you for your help. So far I have this:

    ========
    -
    -

    -- into module
    ser_clkr <= ser_clkr_i;
    ser_clkr_q <= ser_clkr; -- previous val of clkr

    --new serial clock to be generated from input of CLKR.
    new_clk_gen: process(ser_clkr, ser_clkr_q)
    begin
    if (ser_clkr_q = '0' and ser_clkr_q = '1') then
    ser_clkx <= not ser_clkx;
    else
    ser_clkx <= ser_clkx;
    end process;
    vu, Aug 21, 2006
    #1
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  2. vu

    Jerrie85

    Joined:
    Aug 18, 2006
    Messages:
    7
    why dont u just transmit_clk <= ~receive_serial_clock;
    this is just straight inverter, combination logic
    Jerrie85, Aug 22, 2006
    #2
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  3. IMHO I think you've got a bit of work to do... The grass roots of VHDL is
    good synchronous design practice. Ok, of course it can be much more
    complicated that that, but you should start with the idea that you have a
    global system reset, and a global system clock, everything that happens in
    your design is initialised with the reset, and synchronous to the clock.
    every process can then be written as a flip-flop, with combinational logic
    behind it.

    To give you a head-start with what you wrote...

    someprocess : process (clk, rst)
    begin
    if rst = '1' then
    -- here you initialise your signals
    elsif rising_edge (clk) then
    -- here something happens every rising edge of the clock
    end if;
    end process;

    Use this kind of structure to describe your circuit!

    > if (ser_clkr_q = '0' and ser_clkr_q = '1') then


    I'm sure you don't mean this!!

    > ser_clkx <= not ser_clkx;
    > else
    > ser_clkx <= ser_clkx;


    And this creates a latch... not good!

    Go back to basics and consider what is good synchronous design...!!
    A good question to start with is how would you make the circuit if you had a
    drawer full of 7400s, not an FPGA/CPLD?
    Good luck!
    Ben
    Benjamin Todd, Aug 27, 2006
    #3
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