Serial comm from BRAM

Discussion in 'VHDL' started by matchstick86, Feb 19, 2010.

  1. matchstick86

    matchstick86

    Joined:
    Oct 2, 2009
    Messages:
    19
    I have a dual port RAM (both ports 8 x 31250) and I would like to send data stored in each address of Port B via a UART (RS232).

    Here is a little background:
    Port A is written with data while Port B is untouched. Once Port A is full, writing halts and reading from Port B begins. Data from each data is read and sent serially to a terminal at a baud rate of 115200. FPGA is running at 50 MHz. After all data in Port B are read, Port A and Port B addresses are reset to 0's and the process starts over.

    My question is, what is the best way to control how each Port B address is read by the uart module? I have an address counter to keep track of where in Port B we are, but I suspect that while a bit is being sent, the Port B address is increased before all the txd_data bits are sent, thus overwriting read information.

    I hope I'm clear enough. Any tips?
    matchstick86, Feb 19, 2010
    #1
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  2. matchstick86

    matchstick86

    Joined:
    Oct 2, 2009
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    Ok, I seemed to have fixed this issue with supposedly proper handshaking signals where addrA tells port A to stop collecting when it is at its max. In turn, Port B gets the go from addrA to send data from Port A address (in its own Port B addresses. I know how a symmetric dual port RAM look like in VHDL). Once Port B is done with sending, Port B turns off and Port A turns on again.

    now my question, if Port A is 16 x 100 (16 bits, 100 depth) and Port B is 8 x 200 (8 bits, 200 depth), how is data read from Port B?

    Let's say addrA(0) has data[15:0]. Is data[7:0] send from Port B, followed by data[15:8]? I think this should be the most probable case.

    The reason why I am asking is because I have count values that span 16 bits, but since our trusty old-timer RS232 can only send in bytes, there could be some undesirable framing issues (as in, data[15:8] comes out before data[7:0]).
    matchstick86, Mar 9, 2010
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