serial stream data to capture in parallel line

Discussion in 'VHDL' started by JSreeniv, Aug 17, 2009.

  1. JSreeniv

    JSreeniv Guest

    Hi All,
    I am writing VHDL Testbench for Manchester encoding.. i am done with
    the simulation and the results on expected output is complex to
    analyze or identify what message has been transferred

    Description: I am transmitting a message on serial encoded stream
    signal TX_OUT; where it consists the message format:<Start Bit>-<5-Bit
    Header>-<32-Bit Data[29:1]>-<32-Bit check test word>-<32-Bit O.V.P-
    H.W>
    Where O.V.P-H.W: Odd Vertical Parity -Hardware Generated
    So all these fields are encoded using Manchester format. Here start
    Bit is High for 150 ns and Low for 150 ns and the rest of the fields
    are High for 50 ns and Low for 50 ns.(Where the rest of the field bits
    the Manchester form is : 1->10, 0->01)

    I am Writing only Header, data, check test word(which is always having
    value:0x0000 0000). After writing VHDL code for this I am having
    complexity on Simulation window where I can see TX_OUT will have
    serial encoded data with above specified message fields, so to conform
    the exact data is transmitted or not I have to analyze the TX_OUT
    signal stream which is eating more time and chances to miss any bit
    Is there any way to capture the serial encoded stream into any
    register or in parallel and observe the message fields in Hexadecimal
    or at least Binary of written data.
    Please give exposure on this issue.

    Thanks
    JSreeniv, Aug 17, 2009
    #1
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  2. JSreeniv

    JimLewis Guest

    Hi Sreenivas,
    If your design is a transmitter, I would write a model that is a
    receiver. Then have that model either write the value received
    to a file so you can compare results after the simulation finishes,
    or the model can pass the value back up to a higher level in the
    testbench so the received value can be compared with the expected
    value.

    Best,
    Jim

    BTW, we have a class on August 25-28 on VHDL Testbenches and
    Verification that may help you. It is in Beaverton (Portland), OR.
    See http://www.synthworks.com/public_vhdl_courses.htm
    for details.
    JimLewis, Aug 17, 2009
    #2
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  3. JSreeniv

    JSreeniv Guest

    On Aug 17, 9:04 pm, JimLewis <> wrote:
    > Hi Sreenivas,
    > If your design is a transmitter, I would write a model that is a
    > receiver.  Then have that model either write the value received
    > to a file so you can compare results after the simulation finishes,
    > or the model can pass the value back up to a higher level in the
    > testbench so the received value can be compared with the expected
    > value.
    >
    > Best,
    > Jim
    >
    > BTW, we have a class on August 25-28 on VHDL Testbenches and
    > Verification that may help you.  It is in Beaverton (Portland), OR.
    > Seehttp://www.synthworks.com/public_vhdl_courses.htm
    > for details.


    Hi Jim,
    I done simulation for Receiver Model...and i did not get the
    explanation of yours...please discuss a bit more on this.
    Thanks
    JSreeniv, Aug 18, 2009
    #3
  4. JSreeniv

    backhus Guest

    On 18 Aug., 07:43, JSreeniv <> wrote:
    > On Aug 17, 9:04 pm, JimLewis <> wrote:
    >
    > > Hi Sreenivas,
    > > If your design is a transmitter, I would write a model that is a
    > > receiver.  Then have that model either write the value received
    > > to a file so you can compare results after the simulation finishes,
    > > or the model can pass the value back up to a higher level in the
    > > testbench so the received value can be compared with the expected
    > > value.

    >
    > > Best,
    > > Jim

    >
    > > BTW, we have a class on August 25-28 on VHDL Testbenches and
    > > Verification that may help you.  It is in Beaverton (Portland), OR.
    > > Seehttp://www.synthworks.com/public_vhdl_courses.htm
    > > for details.

    >
    > Hi Jim,
    > I done simulation for Receiver Model...and i did not get the
    > explanation of yours...please discuss a bit more on this.
    > Thanks

    Hi Sreenivas,
    Jims approach is kind of a standard procedure for such applications.
    For (hopefully) better understanding I recite it in different words:

    If your device under test is a transmitter that produces a serial
    bitstream, then simply add an instance or a behavioral model (process)
    of the corresponding receiver to your testbench. The receiver converts
    the serial bitstream back to readable words. Additional processes in
    your testbench can automatically check if the received data is the
    same as what you fed into the transmitter before. So in a loop you can
    very easy check a lot of testpatterns automatically without even
    bothering about the waveforms. And when an errpor occurs you have to
    take a deeper look at the serial bitstream anyway, but just for the
    short period that contains the faulty data.

    Have a nice simulation
    Eilert
    backhus, Aug 18, 2009
    #4
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