set tri-state

Discussion in 'VHDL' started by Urban Stadler, Aug 2, 2004.

  1. hi

    i'm using vhdl to implement a design in a xilinx 95144XL.
    how can i set io's to tristate?

    thanks
    urban
     
    Urban Stadler, Aug 2, 2004
    #1
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  2. "Urban Stadler" <> wrote in message news:<DRzPc.94$sh.37@fed1read06>...
    > hi
    >
    > i'm using vhdl to implement a design in a xilinx 95144XL.
    > how can i set io's to tristate?
    >
    > thanks
    > urban


    Hi,

    An example assuming IO-signal "data" is declared as a std_logic_vector:

    data <= idata when oe = '1' else (others => 'Z');

    In this example "idata" is the internal databus and "oe" an output-enable signal.

    /Peter
     
    Peter Hermansson, Aug 3, 2004
    #2
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