set tri-state

[Urban Stadler]

hi

i'm using vhdl to implement a design in a xilinx 95144XL.
how can i set io's to tristate?

thanks
urban

 

[Peter Hermansson]

hi

i'm using vhdl to implement a design in a xilinx 95144XL.
how can i set io's to tristate?

thanks
urban

Hi,

An example assuming IO-signal "data" is declared as a std_logic_vector:

data <= idata when oe = '1' else (others => 'Z');

In this example "idata" is the internal databus and "oe" an output-enable signal.

/Peter