Setting up a tri state buffer in VHDL with 2 clks

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Jun 14, 2010
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HI Guys I have a problem, I have written some tri state code shown below which I can get to work can anyone please assist me in getting this code to work.

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dataflow_control is
port
(
	state_enable		: in    std_logic;
	output_enable	: in    std_logic;
	camera_clk	: in    std_logic;
	readclk		: in    std_logic;
	data_in		: in    std_logic_vector(7 downto 0);
	data_inout	: inout std_logic_vector(7 downto 0);
	data_output	: out   std_logic_vector(7 downto 0)
);
end dataflow_control;

architecture behavior of dataflow_control is

--signal data_in_reg	:std_logic_vector(7 downto 0);
--signal data_out_reg	:std_logic_vector(7 downto 0);

begin

 -- data_in_reg <= data_in when (output_enable = '0') else "ZZZZZZZZ";
-- data_inout <= data_in_reg when (rising_edge(camera_clk));
 -- data_out <= data_inout when (output_enable = '1') else "ZZZZZZZZ" ;


	process(camera_clk,state_enable,data_in,output_enable)
		begin
		if (state_enable = '1' and rising_edge(camera_clk)) then
			if output_enable = '0' then
				data_inout <= data_in;
			else
				data_inout <= "ZZZZZZZZ";
			end if;	
		end if;
	end process;
	
	process(readclk,state_enable,output_enable)
		begin
		if (state_enable = '1' and rising_edge(readclk)) then
			if output_enable <= '1' then
				data_output <= data_inout;
			else
				data_output <= "ZZZZZZZZ";
			end if;
		end if;
	end process;

	-- process(output_enable)
		-- begin
			-- if output_enable = '0' then
				-- data_inout <= data_in_reg;
				-- data_out_reg <= data_inout;
				
				-- data_inout <= "ZZZZZZZZ";
				-- data_out_reg <= data_inout;
			-- else
				-- data_inout <= data_in_reg;
				-- data_out_reg <= data_inout;
			-- end if;	
	-- end process;			
			
end behavior;

I have been realy struggeling to get this to work. I have also tried diffrent variations and some times it synths correctly but when I post synth simulate my output is XXXXXXXXXXX.

I dont know what Iam doing wrong.

And also im getting this error

W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN132 Removing sequential instance stage0.data_inout_cl_6[7], because it is equivalent to instance stage0.data_inout_cl_7[7] dataflow_control.vhd (31) camera_payload_1.srr (57) 22:34:27 Mon Jun 14 ProASIC3E Mapper
W BN246 Failed to find top level module 'work.camera_payload' as specified in project file - camera_payload_1.srr (49) 19:25:15 Mon Jun 14 ProASIC3E Mapper
W BN269 Library ARC pruning: multiple bidi in cell BIBUF_LVDS. Pruning abandoned. - camera_payload_1.srr 15:13:48 Mon Jun 14 ProASIC3E Mapper

Any help whould be greatly appreciated...

Thx
 
Joined
Mar 10, 2008
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Your problems are due to "multiple drivers".
It's not possible to drive the same bus - like data_inout - from more then one process.
 

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