Shared Variables...

Discussion in 'VHDL' started by Element Blue, Oct 24, 2004.

  1. Element Blue

    Element Blue Guest

    Hi All,
    I want to use variables that should be common to various
    processes in a architecture.These variables represent status signals and
    are updated "instantaneously",and must be visible to various processes.How
    do I achieve this ?
    Skeleton Code:
    architecture behave of ename is
    variable status_signal:bit;
    begin
    process1(Clock,In1)
    begin
    if(status_signal) then
    ...
    end if;
    status_signal :='0';
    end process;
    process2(Clock,In2)
    begin
    if(!(status_signal)) then
    ....
    end if;
    status_signal:='1';
    end process;
    end architecture
    This gives a compile error,saying variables need to be shared..How do I
    get both processes to read and write the status signals?
    Thanks a lot,
    Bye
     
    Element Blue, Oct 24, 2004
    #1
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  2. Element Blue wrote:

    > This gives a compile error,saying variables need to be shared..How do I
    > get both processes to read and write the status signals?


    Declare the shared variables in a package for simulation.
    For synthesis use signals.

    -- Mike Treseler
     
    Mike Treseler, Oct 24, 2004
    #2
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  3. Element Blue

    rickman Guest

    Element Blue wrote:
    >
    > Hi All,
    > I want to use variables that should be common to various
    > processes in a architecture.These variables represent status signals and
    > are updated "instantaneously",and must be visible to various processes.How
    > do I achieve this ?
    > Skeleton Code:
    > architecture behave of ename is
    > variable status_signal:bit;
    > begin
    > process1(Clock,In1)
    > begin
    > if(status_signal) then
    > ...
    > end if;
    > status_signal :='0';
    > end process;
    > process2(Clock,In2)
    > begin
    > if(!(status_signal)) then
    > ....
    > end if;
    > status_signal:='1';
    > end process;
    > end architecture
    > This gives a compile error,saying variables need to be shared..How do I
    > get both processes to read and write the status signals?
    > Thanks a lot,
    > Bye


    In this situation, you will not see a difference between a signal and a
    variable. The variable is updated immediately inside the process while
    a signal is not updated until the process halts. But the other process
    will not see the variable until the first process has halted anyway! So
    the result will be the same either way. Besides, if the variable was
    updated immediately and another process run before the first was
    complete, it would be indeterminant as to which ran first and you would
    get indeterminant results.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 24, 2004
    #3
  4. Element Blue

    Element Blue Guest

    On Sun, 24 Oct 2004, rickman wrote:

    > Element Blue wrote:
    >> Skeleton Code:
    >> architecture behave of ename is
    >> variable status_signal:bit;
    >> begin
    >> process1(Clock,In1)
    >> begin
    >> if(status_signal) then
    >> ...
    >> end if;
    >> status_signal :='0';
    >> end process;
    >> process2(Clock,In2)
    >> begin
    >> if(!(status_signal)) then
    >> ....
    >> end if;
    >> status_signal:='1';
    >> end process;
    >> end architecture
    >> This gives a compile error,saying variables need to be shared..How do I
    >> get both processes to read and write the status signals?

    >
    > a signal is not updated until the process halts. But the other process
    > will not see the variable until the first process has halted anyway! So

    Thanks Mike and Rick.
    The 2 processes are a read process and a write process. The memory
    is a "queue".I want simultaneous read and write to be possible,so I wrote
    2 processes,one ofr read and other for write. The 2 processes however need
    to be able to read and update the status signals Empty and
    Full. Moreover,since the 2 processes are running concurrently,I want the
    the change made by one process to be visible immediately to the other,so
    that it may function correctly.
    If I make the variables global,will the other process still not be
    able to see the new value until the first process suspends? I think my
    larger problem is of communicating between two processes..
    Thanks.

    > the result will be the same either way. Besides, if the variable was
    > updated immediately and another process run before the first was
    > complete, it would be indeterminant as to which ran first and you would
    > get indeterminant results.


    >
    > --
    >
    > Rick "rickman" Collins
    >
    >
    > Ignore the reply address. To email me use the above address with the XY
    > removed.
    >
    > Arius - A Signal Processing Solutions Company
    > Specializing in DSP and FPGA design URL http://www.arius.com
    > 4 King Ave 301-682-7772 Voice
    > Frederick, MD 21701-3110 301-682-7666 FAX
    >
     
    Element Blue, Oct 25, 2004
    #4
  5. Element Blue

    rickman Guest

    Element Blue wrote:
    >
    > The 2 processes are a read process and a write process. The memory
    > is a "queue".I want simultaneous read and write to be possible,so I wrote
    > 2 processes,one ofr read and other for write. The 2 processes however need
    > to be able to read and update the status signals Empty and
    > Full. Moreover,since the 2 processes are running concurrently,I want the
    > the change made by one process to be visible immediately to the other,so
    > that it may function correctly.
    > If I make the variables global,will the other process still not be
    > able to see the new value until the first process suspends? I think my
    > larger problem is of communicating between two processes..
    > Thanks.


    If I can assume you are writing for synthesis, I feel you are thinking
    the wrong way. You are trying to design a VHDL program and not thinking
    at all about what hardware will be produced. I suggest, as I seem to do
    often lately, that you design in terms of the hardware that will do the
    job you want. Then write HDL code to describe the registers, counters
    and memory that you want. The HDL is designed to "describe" hardware.
    If you do that, a lot of the issues you are having trouble with will
    become very clear.

    Designing a queue is not overly hard if both sides use the same clock.
    I use three counters; one to point to the read location, one to the
    write location and a third for counting. There are four possible input
    combinations; idle, read, write and both read and write. The status
    flags (internal signals) can be; empty, full or neither. The design of
    what happens when and to what is not too hard, but you have to make a
    few decisions about what to do under error conditions such as writing to
    a "full" FIFO. Do you write and clobber read data, or do you drop the
    write data?

    The rest should be easy enough. FIFOs (queues) get hard when the two
    clocks are asynchronous.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 26, 2004
    #5
  6. Strictly of course, the question of how to handle invalid inputs
    belongs in the *specification*, rather than the design phase. But
    often these are blurred :)

    rickman <> wrote:
    [snip]
    : The design of
    :what happens when and to what is not too hard, but you have to make a
    :few decisions about what to do under error conditions such as writing to
    :a "full" FIFO. Do you write and clobber read data, or do you drop the
    :write data?
    :
    :The rest should be easy enough. FIFOs (queues) get hard when the two
    :clocks are asynchronous.
     
    David R Brooks, Oct 26, 2004
    #6
  7. Element Blue

    ALuPin Guest

    Hi,

    try to get an idea of how a FIFO works.

    At www.vhdl-online.de -->model-lib Patras

    there is some VHDL code (including simulation files)
    for a FIFO with one clock and a FIFO with two clocks.

    If you use Altera or Xilinx you could also define
    your FIFO with a template.

    Rgds

    André
     
    ALuPin, Oct 26, 2004
    #7
  8. Element Blue

    Element Blue Guest

    On Tue, 26 Oct 2004, ALuPin wrote:

    > Hi,
    >
    > try to get an idea of how a FIFO works.
    >
    > At www.vhdl-online.de -->model-lib Patras
    >
    > there is some VHDL code (including simulation files)
    > for a FIFO with one clock and a FIFO with two clocks.


    Thanks Rick..definitely cleared up a few problems.As for writing
    to a full FIFO , the handshake signals wll not allow a write to proceed in
    that case.Anyway,I am a lot clearer now on what to do :)
    Thanks ALuPin for the link..very useful sample codes there.
    Regards,
    EB.
    >
    > If you use Altera or Xilinx you could also define
    > your FIFO with a template.
    >
    > Rgds
    >
    > André
    >
     
    Element Blue, Oct 26, 2004
    #8
  9. Element Blue <> wrote in message news:<>...

    > Thanks Mike and Rick.
    > The 2 processes are a read process and a write process. The memory
    > is a "queue".I want simultaneous read and write to be possible,so I wrote
    > 2 processes,one ofr read and other for write. The 2 processes however need
    > to be able to read and update the status signals Empty and
    > Full.


    Two gates cannot drive the same output.
    Two processes cannot drive the same signal.
    However, one process can handle all of your data
    and flag assignments. See:

    http://groups.google.com/groups?q=vhdl fifo code gvaglia

    Remember that even though
    a process is written sequentially, each statement
    requires zero execution time. You will get
    parallel processing in either case.

    -- Mike Treseler
     
    Mike Treseler, Oct 26, 2004
    #9
  10. Element Blue

    Raghavendra Guest

    Hi,

    Here you are driving a signal from two sources.Variable are local
    to process block.For synthesis you need to use signals.Otherwise you
    can combine the two process and maintain the same functionality.

    Raghavendra.Sortur

    Element Blue <> wrote in message news:<>...
    > On Sun, 24 Oct 2004, rickman wrote:
    >
    > > Element Blue wrote:
    > >> Skeleton Code:
    > >> architecture behave of ename is
    > >> variable status_signal:bit;
    > >> begin
    > >> process1(Clock,In1)
    > >> begin
    > >> if(status_signal) then
    > >> ...
    > >> end if;
    > >> status_signal :='0';
    > >> end process;
    > >> process2(Clock,In2)
    > >> begin
    > >> if(!(status_signal)) then
    > >> ....
    > >> end if;
    > >> status_signal:='1';
    > >> end process;
    > >> end architecture
    > >> This gives a compile error,saying variables need to be shared..How do I
    > >> get both processes to read and write the status signals?

    > >
    > > a signal is not updated until the process halts. But the other process
    > > will not see the variable until the first process has halted anyway! So

    > Thanks Mike and Rick.
    > The 2 processes are a read process and a write process. The memory
    > is a "queue".I want simultaneous read and write to be possible,so I wrote
    > 2 processes,one ofr read and other for write. The 2 processes however need
    > to be able to read and update the status signals Empty and
    > Full. Moreover,since the 2 processes are running concurrently,I want the
    > the change made by one process to be visible immediately to the other,so
    > that it may function correctly.
    > If I make the variables global,will the other process still not be
    > able to see the new value until the first process suspends? I think my
    > larger problem is of communicating between two processes..
    > Thanks.
    >
    > > the result will be the same either way. Besides, if the variable was
    > > updated immediately and another process run before the first was
    > > complete, it would be indeterminant as to which ran first and you would
    > > get indeterminant results.

    >
    > >
    > > --
    > >
    > > Rick "rickman" Collins
    > >
    > >
    > > Ignore the reply address. To email me use the above address with the XY
    > > removed.
    > >
    > > Arius - A Signal Processing Solutions Company
    > > Specializing in DSP and FPGA design URL http://www.arius.com
    > > 4 King Ave 301-682-7772 Voice
    > > Frederick, MD 21701-3110 301-682-7666 FAX
    > >
     
    Raghavendra, Oct 27, 2004
    #10
  11. Element Blue

    vlsi.vishal

    Joined:
    Jan 17, 2012
    Messages:
    1
    Shared Variables in VHDL'93

    VHDL87 limited the scope of the variable to the process in which it was declared.:trytofly:
    VHDL '93 introduced shared variables which are available to more than one process. Like ordinary VHDL variables.:bored:

    more on shared variables can be find on
    http://vlsiencyclopedia.blogspot.com/2012/01/shared-variable-in-vhdl.html

    with the same example i had explained it.
     
    vlsi.vishal, Jan 17, 2012
    #11
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