Shift arithmetic problem for noob

[jeucomanu]

hi everybody,

how i can traslate this line in C

varA = (varA<<4) + varB;

in VHDL language????

wrong exemple

varA <= (varA sll 4) + varB;

My problem is the shift "<<" i try with SHL, sll, ecc. but i cant
compile the vhdl because there is some error.
I have include librerie std_logic_arith "use
IEEE.std_logic_arith.all;" but have this error:

Operator "sll" is not defined for such operands.
Undefined type of expression.
Assignment target incompatible with right side. Expected type
"std_logic_vector".

i have tray with different type: std_logic_vector, integer, bit_vector
but i have the same result, error on compile.

pls, help me.

Jeuco

 

[KJ]

hi everybody,

how i can traslate this line in C

varA = (varA<<4) + varB;

in VHDL language????

wrong exemple

varA <= (varA sll 4) + varB;

My problem is the shift "<<" i try with SHL, sll, ecc. but i cant
compile the vhdl because there is some error.
I have include librerie std_logic_arith "use
IEEE.std_logic_arith.all;" but have this error:

Operator "sll" is not defined for such operands.
Undefined type of expression.
Assignment target incompatible with right side. Expected type
"std_logic_vector".

i have tray with different type: std_logic_vector, integer, bit_vector
but i have the same result, error on compile.

Don't use std_logic_arith, use numeric_std instead.....and take a look at
the shift_left function it does exactly what you want

KJ

 

[Andy]

Don't use std_logic_arith, use numeric_std instead.....and take a look at
the shift_left function it does exactly what you want

KJ

As does multiplication by a constant power of two for integer or
numeric_std.signed/unsigned:

varA <= varA * 2**4 + varB;

If the length of varB is also 4 (or less), then the arithmetic will
optimize out to just bit stuffing.

Andy

 

[jeucomanu]

As does multiplication by a constant power of two for integer or
numeric_std.signed/unsigned:

varA <= varA * 2**4 + varB;

If the length of varB is also 4 (or less), then the arithmetic will
optimize out to just bit stuffing.

Andy

Ok, i now this trick and there are another solution for bypass the
problem but i want know why sll don't work and resolve the problem for
use sll or SHl?

anybody can explain me?

 

[Mike Treseler]

Ok, i now this trick and there are another solution for bypass the
problem but i want know why sll don't work and resolve the problem for
use sll or SHl?

anybody can explain me?

http://groups.google.com/groups/search?q=sll+shifter+po_v

 

[jeucomanu]

http://groups.google.com/groups/search?q=sll+shifter+po_v

but you read what i wrote? i don't want a trick o different solution,
i want know why i cant compile vhdl whit operator SLL or SHL

 

[KJ]

but you read what i wrote? i don't want a trick o different solution,
i want know why i cant compile vhdl whit operator SLL or SHL

Well gee, you don't post your code and you expect people to tell you why
your code doesn't compile? The data types matter, and the error messages
that you are getting were telling you that the data types are not correct.
Like all other functions and procedures, 'sll' expects certain data types
as inputs and produces certain data types as outputs. Those definitions are
not secrets, do a search for the the function definition of 'sll' and you
will see what data types it expects and produces.

For some sample code that uses sll in a manner similar to how you listed in
your code snippet at the start of the thread, see below. It compiles and
works so look at how your code differs from it...that is a likely source of
your error.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
end foo;

architecture RTL of foo is
signal Vara, Varb, Varc: unsigned(7 downto 0);
begin
Vara <= "00000001";
Varb <= "00000010";
Varc <= (Vara sll 4) + Varb;
end RTL;

KJ