Shift register extraction fails

Discussion in 'VHDL' started by Philip Herzog, May 29, 2008.

  1. Hi!

    I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
    Spartan 3E. I'm down to copying this code:

    entity shift is
    port(C, SI : in std_logic;
    SO : out std_logic);
    end shift;
    architecture archi of shift is
    signal tmp: std_logic_vector(7 downto 0);
    begin
    process (C)
    begin
    if (C'event and C='1') then
    for i in 0 to 6 loop
    tmp(i+1) <= tmp(i);
    end loop;
    tmp(0) <= SI;
    end if;
    end process;
    SO <= tmp(7);
    end archi;

    from the xilinx website:
    http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02007.htm

    But still, ISE synthesizes D-Flipflops:
    Synthesizing Unit <shift>.
    Related source file is "...".
    Found 8-bit register for signal <tmp>.
    Summary:
    inferred 8 D-type flip-flop(s).
    Unit <shift> synthesized.

    And yes, Shift register extraction and logical shifter extraction in the
    HDL options are checked.

    Please, help me before I go mad...

    - Philip
    --
    Machen Sie sich erst einmal unbeliebt, dann werden
    Sie auch ernst genommen. (Konrad Adenauer)
     
    Philip Herzog, May 29, 2008
    #1
    1. Advertising

  2. Philip Herzog

    Symon Guest

    "Philip Herzog" <> wrote in message
    news:...
    > Hi!
    >
    > I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
    > Spartan 3E. I'm down to copying this code:
    >
    >
    > And yes, Shift register extraction and logical shifter extraction in the
    > HDL options are checked.
    >
    > Please, help me before I go mad...
    >
    > - Philip
    > --
    > Machen Sie sich erst einmal unbeliebt, dann werden
    > Sie auch ernst genommen. (Konrad Adenauer)
    >

    Hi Philip,

    Does this work? :-

    tmp <= tmp(6 downto 0) & SI;

    HTH., Syms.
     
    Symon, May 29, 2008
    #2
    1. Advertising

  3. Symon wrote:
    > Does this work? :-
    > tmp <= tmp(6 downto 0) & SI;


    Nope, tried that too...

    - Philip
    --
    Machen Sie sich erst einmal unbeliebt, dann werden
    Sie auch ernst genommen. (Konrad Adenauer)
     
    Philip Herzog, May 29, 2008
    #3
  4. Brian Drummond wrote:
    > Does the synthesiser recognise the preferred
    > if rising_edge(C) then
    > instead?


    Yes, that's what I usually use. I just copied this example from the
    xilinx web page because that was the example they gave for shift
    register extraction.

    - Philip
    --
    Machen Sie sich erst einmal unbeliebt, dann werden
    Sie auch ernst genommen. (Konrad Adenauer)
     
    Philip Herzog, May 29, 2008
    #4
  5. Philip Herzog

    Symon Guest

    Philip,
    Webcase?
    Syms.
     
    Symon, May 29, 2008
    #5
  6. Philip Herzog wrote:
    > I'm trying to get Xilinx ISE 9.2 to synthesize a shift register
    > But still, ISE synthesizes D-Flipflops:
    > Synthesizing Unit <shift>.
    > Related source file is "...".
    > Found 8-bit register for signal <tmp>.
    > Summary:
    > inferred 8 D-type flip-flop(s).


    > And yes, Shift register extraction and logical shifter extraction in the
    > HDL options are checked.
    >
    > Please, help me before I go mad...


    Maybe those 8 flops are wired up like a shift register.
    Have a look on the RTL viewer.

    Note that all the fpga really has is luts and flops.
    A shift register is an abstraction.

    -- Mike Treseler
     
    Mike Treseler, May 29, 2008
    #6
  7. Philip Herzog

    jens Guest

    It looks like that part only supports a 16-bit shift register in a LUT.
     
    jens, May 29, 2008
    #7
  8. Philip Herzog

    Symon Guest

    "jens" <> wrote in message
    news:...
    > It looks like that part only supports a 16-bit shift register in a LUT.


    No,
    UG331
    Fig.7.2.
    Syms.
     
    Symon, May 30, 2008
    #8
  9. Mike Treseler wrote:
    > Maybe those 8 flops are wired up like a shift register.


    I'm pretty sure they were, but that's the whole point: That uses 8
    flops, but if the shift register was extracted and packed into a LUT I'd
    only use one LUT. This makes a difference for me, since I need many of
    them...

    - Philip
    --
    I will always be puzzled by the human predilection
    for piloting vehicles at unsafe velocities.
    (Lieutenant Commander Data)
     
    Philip Herzog, May 30, 2008
    #9
  10. Philip Herzog

    Tricky Guest

    On 30 May, 08:29, Philip Herzog <> wrote:
    > Mike Treseler wrote:
    > > Maybe those 8 flops are wired up like a shift register.

    >
    > I'm pretty sure they were, but that's the whole point: That uses 8
    > flops, but if the shift register was extracted and packed into a LUT I'd
    > only use one LUT. This makes a difference for me, since I need many of
    > them...
    >
    > - Philip
    > --
    > I will always be puzzled by the human predilection
    > for piloting vehicles at unsafe velocities.
    > (Lieutenant Commander Data)


    A LUT "shift register" as you call it is not actually a shift
    register, rather it is a delay function. You cannnot tap off it. The
    Unisim library contains an element "SRL16", which will implement a 1
    bit shift register that takes 1 lut, with a delay of between 1 and 16
    clock cycles. It uses 1 Lut and 1 register.

    The problem with delcaring it as a vector of length 16, it implies
    each bit is a register, and you have access to each bit individually.
    Unless the synthesiser analyses the registers and finds none of them
    are tapped, and is clever enough, it will most likely create a string
    of registers.
     
    Tricky, May 30, 2008
    #10
  11. Tricky wrote:
    > A LUT "shift register" as you call it is not actually a shift
    > register, rather it is a delay function. You cannnot tap off it.


    SRLC16E - yes I can.

    Plus, if the xilinx website gives an example code and states it will be
    synthesized into a shift register it is possible - I hope, at least.

    I did implement it by instantiating an SRLC16E, and it works - but why
    does the synthesis of the VHDL code not work as stated?

    - Philip
    --
    I will always be puzzled by the human predilection
    for piloting vehicles at unsafe velocities.
    (Lieutenant Commander Data)
     
    Philip Herzog, May 30, 2008
    #11
  12. Philip Herzog wrote:
    > Mike Treseler wrote:
    >> Maybe those 8 flops are wired up like a shift register.

    >
    > I'm pretty sure they were, but that's the whole point: That uses 8
    > flops, but if the shift register was extracted and packed into a LUT I'd
    > only use one LUT. This makes a difference for me, since I need many of
    > them...


    In that case, you have found a bug
    and Symon's advice applies.

    I would try the design first
    with generic, inferred shifters
    and see if it doesn't just fit anyway.

    If it does, you have a portable, readable design
    with full-speed registers and
    you can let someone else fuss
    with the the half-fast version.

    -- Mike Treseler
     
    Mike Treseler, May 30, 2008
    #12
  13. Philip Herzog wrote:
    > Hi!
    >
    > I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
    > Spartan 3E. I'm down to copying this code:
    >
    > entity shift is
    > port(C, SI : in std_logic;
    > SO : out std_logic);
    > end shift;
    > architecture archi of shift is
    > signal tmp: std_logic_vector(7 downto 0);
    > begin
    > process (C)
    > begin
    > if (C'event and C='1') then
    > for i in 0 to 6 loop
    > tmp(i+1) <= tmp(i);
    > end loop;
    > tmp(0) <= SI;
    > end if;
    > end process;
    > SO <= tmp(7);
    > end archi;
    >
    > from the xilinx website:
    > http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02007.htm
    >
    > But still, ISE synthesizes D-Flipflops:
    > Synthesizing Unit <shift>.
    > Related source file is "...".
    > Found 8-bit register for signal <tmp>.
    > Summary:
    > inferred 8 D-type flip-flop(s).
    > Unit <shift> synthesized.
    >
    > And yes, Shift register extraction and logical shifter extraction in the
    > HDL options are checked.
    >
    > Please, help me before I go mad...
    >
    > - Philip


    Philip:
    I put this code in ISE 10.1 and got the same message. However, the
    message is erroneous or ambiguous and the synthesizer is actually using
    an SRL. The design is actually implemented using one SRL (with a delay
    of 5) and an input and output flop (to improve timing, since the i/o
    connect to pins).

    Look at the technology schematic to prove this. Also, if you look at
    the utilization report section of the XST log file, you should see this:

    Slice Logic Utilization:
    Number of Slice Registers: 2 out of 19200 0%
    Number of Slice LUTs: 1 out of 19200 0%
    Number used as Memory: 1 out of 5120 0%
    Number used as SRL: 1

    I have found that you can sometimes use better style than the templates
    in the XST user's guide and they still synthesize properly. This code,
    which I think is better style, synthesizes the same way:

    library ieee;
    use ieee.std_logic_1164.all;
    entity shift_registers_1 is
    port(C, SI : in std_logic;
    SO : out std_logic);
    end shift_registers_1;
    architecture archi of shift_registers_1 is
    signal SI_dly : std_logic_vector(7 downto 0);
    begin
    process (C)
    begin
    if (rising_edge(C)) then
    SI_dly <= SI_dly(6 downto 0) & SI;
    end if;
    end process;
    SO <= SI_dly(7);
    end archi;

    -Kevin
     
    Kevin Neilson, May 30, 2008
    #13
  14. Kevin Neilson wrote:

    > I put this code in ISE 10.1 and got the same message. However, the
    > message is erroneous or ambiguous and the synthesizer is actually using
    > an SRL.


    I expect that the *mapper* step
    decided to utilize a LUT shifter
    to cover the 8 D-type flops
    inferred by synthesis.

    -- Mike Treseler
     
    Mike Treseler, May 30, 2008
    #14
  15. Philip Herzog

    Sean Durkin Guest

    Kevin Neilson wrote:
    > I have found that you can sometimes use better style than the
    > templates in the XST user's guide and they still synthesize properly.
    > This code, which I think is better style, synthesizes the same way:


    > library ieee;
    > use ieee.std_logic_1164.all;
    > entity shift_registers_1 is
    > port(C, SI : in std_logic;
    > SO : out std_logic);
    > end shift_registers_1;
    > architecture archi of shift_registers_1 is
    > signal SI_dly : std_logic_vector(7 downto 0);
    > begin
    > process (C)
    > begin
    > if (rising_edge(C)) then
    > SI_dly <= SI_dly(6 downto 0) & SI;
    > end if;
    > end process;
    > SO <= SI_dly(7);
    > end archi;


    I like this style even better, since you only have to change one single
    line of code (the signal declaration) when you want to change the delay
    later on:

    library ieee;
    use ieee.std_logic_1164.all;
    entity shift_registers_1 is
    port(C, SI : in std_logic;
    SO : out std_logic);
    end shift_registers_1;
    architecture archi of shift_registers_1 is
    signal SI_dly : std_logic_vector(7 downto 0);
    begin
    process (C)
    begin
    if (rising_edge(C)) then
    SI_dly <= SI_dly(SI_dly'length-2 downto 0) & SI;
    end if;
    end process;
    SO <= SI_dly(SI_dly'left);
    end archi;

    This also works if you later decide to pass the length of SI_dly as a
    GENERIC when instantiating the thing.

    cu,
    Sean
     
    Sean Durkin, May 30, 2008
    #15
  16. Mike Treseler wrote:
    > Kevin Neilson wrote:
    >
    >> I put this code in ISE 10.1 and got the same message. However, the
    >> message is erroneous or ambiguous and the synthesizer is actually using
    >> an SRL.

    >
    > I expect that the *mapper* step
    > decided to utilize a LUT shifter
    > to cover the 8 D-type flops
    > inferred by synthesis.
    >
    > -- Mike Treseler
    >

    I'm not sure what you mean by "mapper": I think of "map.exe" (in the
    Xilinx flow) as "the mapper". Some people refer to a stage within the
    synthesizer as the mapper. -Kevin
     
    Kevin Neilson, May 30, 2008
    #16
  17. Philip Herzog

    Symon Guest

    "Kevin Neilson" <> wrote in message
    news:g1pmbj$...
    > Mike Treseler wrote:
    >> Kevin Neilson wrote:
    >>
    >>> I put this code in ISE 10.1 and got the same message. However, the
    >>> message is erroneous or ambiguous and the synthesizer is actually using
    >>> an SRL.

    >>
    >> I expect that the *mapper* step
    >> decided to utilize a LUT shifter
    >> to cover the 8 D-type flops
    >> inferred by synthesis.
    >>
    >> -- Mike Treseler
    >>

    > I'm not sure what you mean by "mapper": I think of "map.exe" (in the
    > Xilinx flow) as "the mapper". Some people refer to a stage within the
    > synthesizer as the mapper. -Kevin


    Hi Kev,
    What? Look at your results and tell us the answer!
    Thanks, Syms.
     
    Symon, May 31, 2008
    #17
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Roberto Gallo

    Shift - byte[] buf shift

    Roberto Gallo, Jan 27, 2004, in forum: Java
    Replies:
    3
    Views:
    2,073
    Thomas Schodt
    Jan 27, 2004
  2. Wenjie
    Replies:
    3
    Views:
    1,040
    Ron Samuel Klatchko
    Jul 11, 2003
  3. Santosh Nayak

    Left Shift / Right Shift Operators

    Santosh Nayak, Nov 30, 2006, in forum: C Programming
    Replies:
    16
    Views:
    1,458
    CBFalconer
    Nov 30, 2006
  4. Sanny
    Replies:
    38
    Views:
    3,425
    Thomas Richter
    Apr 29, 2011
  5. devphylosoff

    what "shift" does, if not "$_ = shift;" ?

    devphylosoff, Nov 29, 2007, in forum: Perl Misc
    Replies:
    3
    Views:
    334
    Michele Dondi
    Dec 4, 2007
Loading...

Share This Page