Shift register extraction fails

[Philip Herzog]

Hi!

I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
Spartan 3E. I'm down to copying this code:

entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;

from the xilinx website:
http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02007.htm

But still, ISE synthesizes D-Flipflops:
Synthesizing Unit <shift>.
Related source file is "...".
Found 8-bit register for signal <tmp>.
Summary:
inferred 8 D-type flip-flop(s).
Unit <shift> synthesized.

And yes, Shift register extraction and logical shifter extraction in the
HDL options are checked.

Please, help me before I go mad...

- Philip

 

[Symon]

Hi!

I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
Spartan 3E. I'm down to copying this code:


And yes, Shift register extraction and logical shifter extraction in the
HDL options are checked.

Please, help me before I go mad...

- Philip

Hi Philip,

Does this work? :-

tmp <= tmp(6 downto 0) & SI;

HTH., Syms.

 

[Philip Herzog]

Does this work? :-
tmp <= tmp(6 downto 0) & SI;

Nope, tried that too...

- Philip

 

[Philip Herzog]

Does the synthesiser recognise the preferred
if rising_edge(C) then
instead?

Yes, that's what I usually use. I just copied this example from the
xilinx web page because that was the example they gave for shift
register extraction.

- Philip

 

[Symon]

Philip,
Webcase?
Syms.

 

[Mike Treseler]

I'm trying to get Xilinx ISE 9.2 to synthesize a shift register
But still, ISE synthesizes D-Flipflops:
Synthesizing Unit <shift>.
Related source file is "...".
Found 8-bit register for signal <tmp>.
Summary:
inferred 8 D-type flip-flop(s).

And yes, Shift register extraction and logical shifter extraction in the
HDL options are checked.

Please, help me before I go mad...

Maybe those 8 flops are wired up like a shift register.
Have a look on the RTL viewer.

Note that all the fpga really has is luts and flops.
A shift register is an abstraction.

-- Mike Treseler

 

[jens]

It looks like that part only supports a 16-bit shift register in a LUT.

 

[Symon]

It looks like that part only supports a 16-bit shift register in a LUT.

No,
UG331
Fig.7.2.
Syms.

 

[Philip Herzog]

Maybe those 8 flops are wired up like a shift register.

I'm pretty sure they were, but that's the whole point: That uses 8
flops, but if the shift register was extracted and packed into a LUT I'd
only use one LUT. This makes a difference for me, since I need many of
them...

- Philip

 

[Tricky]

I'm pretty sure they were, but that's the whole point: That uses 8
flops, but if the shift register was extracted and packed into a LUT I'd
only use one LUT. This makes a difference for me, since I need many of
them...

- Philip

A LUT "shift register" as you call it is not actually a shift
register, rather it is a delay function. You cannnot tap off it. The
Unisim library contains an element "SRL16", which will implement a 1
bit shift register that takes 1 lut, with a delay of between 1 and 16
clock cycles. It uses 1 Lut and 1 register.

The problem with delcaring it as a vector of length 16, it implies
each bit is a register, and you have access to each bit individually.
Unless the synthesiser analyses the registers and finds none of them
are tapped, and is clever enough, it will most likely create a string
of registers.

 

[Philip Herzog]

A LUT "shift register" as you call it is not actually a shift
register, rather it is a delay function. You cannnot tap off it.

SRLC16E - yes I can.

Plus, if the xilinx website gives an example code and states it will be
synthesized into a shift register it is possible - I hope, at least.

I did implement it by instantiating an SRLC16E, and it works - but why
does the synthesis of the VHDL code not work as stated?

- Philip

 

[Mike Treseler]

I'm pretty sure they were, but that's the whole point: That uses 8
flops, but if the shift register was extracted and packed into a LUT I'd
only use one LUT. This makes a difference for me, since I need many of
them...

In that case, you have found a bug
and Symon's advice applies.

I would try the design first
with generic, inferred shifters
and see if it doesn't just fit anyway.

If it does, you have a portable, readable design
with full-speed registers and
you can let someone else fuss
with the the half-fast version.

-- Mike Treseler

 

[Kevin Neilson]

Hi!

I'm trying to get Xilinx ISE 9.2 to synthesize a shift register for a
Spartan 3E. I'm down to copying this code:

entity shift is
port(C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;

from the xilinx website:
http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02007.htm

But still, ISE synthesizes D-Flipflops:
Synthesizing Unit <shift>.
Related source file is "...".
Found 8-bit register for signal <tmp>.
Summary:
inferred 8 D-type flip-flop(s).
Unit <shift> synthesized.

And yes, Shift register extraction and logical shifter extraction in the
HDL options are checked.

Please, help me before I go mad...

- Philip

Philip:
I put this code in ISE 10.1 and got the same message. However, the
message is erroneous or ambiguous and the synthesizer is actually using
an SRL. The design is actually implemented using one SRL (with a delay
of 5) and an input and output flop (to improve timing, since the i/o
connect to pins).

Look at the technology schematic to prove this. Also, if you look at
the utilization report section of the XST log file, you should see this:

Slice Logic Utilization:
Number of Slice Registers: 2 out of 19200 0%
Number of Slice LUTs: 1 out of 19200 0%
Number used as Memory: 1 out of 5120 0%
Number used as SRL: 1

I have found that you can sometimes use better style than the templates
in the XST user's guide and they still synthesize properly. This code,
which I think is better style, synthesizes the same way:

library ieee;
use ieee.std_logic_1164.all;
entity shift_registers_1 is
port(C, SI : in std_logic;
SO : out std_logic);
end shift_registers_1;
architecture archi of shift_registers_1 is
signal SI_dly : std_logic_vector(7 downto 0);
begin
process (C)
begin
if (rising_edge(C)) then
SI_dly <= SI_dly(6 downto 0) & SI;
end if;
end process;
SO <= SI_dly(7);
end archi;

-Kevin

 

[Mike Treseler]

I put this code in ISE 10.1 and got the same message. However, the
message is erroneous or ambiguous and the synthesizer is actually using
an SRL.

I expect that the *mapper* step
decided to utilize a LUT shifter
to cover the 8 D-type flops
inferred by synthesis.

-- Mike Treseler

 

[Sean Durkin]

I have found that you can sometimes use better style than the
templates in the XST user's guide and they still synthesize properly.
This code, which I think is better style, synthesizes the same way:

library ieee;
use ieee.std_logic_1164.all;
entity shift_registers_1 is
port(C, SI : in std_logic;
SO : out std_logic);
end shift_registers_1;
architecture archi of shift_registers_1 is
signal SI_dly : std_logic_vector(7 downto 0);
begin
process (C)
begin
if (rising_edge(C)) then
SI_dly <= SI_dly(6 downto 0) & SI;
end if;
end process;
SO <= SI_dly(7);
end archi;

I like this style even better, since you only have to change one single
line of code (the signal declaration) when you want to change the delay
later on:

library ieee;
use ieee.std_logic_1164.all;
entity shift_registers_1 is
port(C, SI : in std_logic;
SO : out std_logic);
end shift_registers_1;
architecture archi of shift_registers_1 is
signal SI_dly : std_logic_vector(7 downto 0);
begin
process (C)
begin
if (rising_edge(C)) then
SI_dly <= SI_dly(SI_dly'length-2 downto 0) & SI;
end if;
end process;
SO <= SI_dly(SI_dly'left);
end archi;

This also works if you later decide to pass the length of SI_dly as a
GENERIC when instantiating the thing.

cu,
Sean

 

[Kevin Neilson]

I expect that the *mapper* step
decided to utilize a LUT shifter
to cover the 8 D-type flops
inferred by synthesis.

-- Mike Treseler

I'm not sure what you mean by "mapper": I think of "map.exe" (in the
Xilinx flow) as "the mapper". Some people refer to a stage within the
synthesizer as the mapper. -Kevin

 

[Symon]

I'm not sure what you mean by "mapper": I think of "map.exe" (in the
Xilinx flow) as "the mapper". Some people refer to a stage within the
synthesizer as the mapper. -Kevin

Hi Kev,
What? Look at your results and tell us the answer!
Thanks, Syms.