Shift registers

Discussion in 'VHDL' started by gervaz, Feb 16, 2009.

  1. gervaz

    gervaz Guest

    Hi all, I'm using shift registers in order to instantiate multiple
    cores in my system. I'm a newbie and I would like to know if my
    approach is correct. Every instance of the core have a shift reg that
    provide the data input and another sifth reg that takes the data
    output. I use the generate statement to connect all my instances to
    the various shft registers.

    This is the code (I want to instantiate multiple Aquarius cores --
    found on opencores.org). Can you please provide me feedback? Thanks

    -------------------------------------------------------------------------------------------------------------------
    --- multi_instance_aquarius
    -------------------------------------------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;


    entity multi_instance is
    generic (
    NINSTANCES : integer := 1;
    NINPUT : integer := 15;
    NOUTPUT : integer := 18
    );

    port (
    CLK: in std_logic;
    RST: in std_logic;
    SHIFTIN: in std_logic_vector (0 to NINSTANCES-1);
    SHIFTOUT: out std_logic_vector (0 to NINSTANCES-1);
    ALOAD: in std_logic
    );
    end multi_instance;

    architecture arch of multi_instance is

    component shiftregINCOMP is
    generic (
    NINPUT : integer := 15
    );
    port (CLK, RST: in std_logic;
    DATAin: in std_logic;
    DATAout: out std_logic_vector (NINPUT-1 downto 0)
    );
    end component;

    component shiftregOUTCOMP is
    generic (
    NOUTPUT : integer := 18
    );
    port (CLK, RST: in std_logic;
    DATAin: in std_logic_vector (NOUTPUT-1 downto 0);
    DATAout: out std_logic;
    ALOAD : in std_logic
    );
    end component;

    component top is port (

    CLK_SRC : in std_logic;
    RST_n : in std_logic;
    LCDDBI : in std_logic_vector (7 downto 0);
    KEYXI : in std_logic_vector (4 downto 0);
    RXD : in std_logic;
    CTS : in std_logic;
    LCDRS : out std_logic;
    LCDRW : out std_logic;
    LCDE : out std_logic;
    LCDDBO : out std_logic_vector (7 downto 0);
    KEYYO : out std_logic_vector (4 downto 0);
    TXD : out std_logic;
    RTS : out std_logic
    );
    end component;

    type shiftregIN is array (NINSTANCES-1 downto 0) of std_logic_vector
    (NINPUT-1 downto 0);
    type shiftregOUT is array (NINSTANCES-1 downto 0) of std_logic_vector
    (NOUTPUT-1 downto 0);
    signal DATAin : shiftregIN;
    signal DATAout : shiftregOUT;

    begin

    generate_inst: for I in 0 to NINSTANCES-1 generate

    top_inst : top
    port map (
    CLK_SRC => CLK,
    RST_n => RST,
    --------------------------------------------------------
    LCDDBI => DATAin(I) (NINPUT-1 downto NINPUT-8),
    KEYXI => DATAin(I) (NINPUT-9 downto NINPUT-13),
    RXD => DATAin(I) (NINPUT-14),
    CTS => DATAin(I) (NINPUT-15),
    --------------------------------------------------------
    LCDRS => DATAout(I) (NOUTPUT-1),
    LCDRW => DATAout(I) (NOUTPUT-2),
    LCDE => DATAout(I) (NOUTPUT-3),
    LCDDBO => DATAout(I) (NOUTPUT-4 downto NOUTPUT-11),
    KEYYO => DATAout(I) (NOUTPUT-12 downto NOUTPUT-16),
    TXD =>DATAout(I) (NOUTPUT-17),
    RTS => DATAout(I) (NOUTPUT-18)
    );

    shiftregIN_inst : shiftregINCOMP
    generic map (NINPUT => NINPUT)

    port map (
    CLK => CLK,
    RST => RST,
    DATAin => SHIFTIN(I),
    DATAout => DATAin(I)
    );

    shiftregOUT_inst : shiftregOUTCOMP
    generic map (NOUTPUT => NOUTPUT)

    port map (
    CLK => CLK,
    RST => RST,
    ALOAD => ALOAD,
    DATAin => DATAout(I),
    DATAout => SHIFTOUT(I)
    );

    end generate;

    end arch;

    -------------------------------------------------------------------------------------------------------------------
    -- shiftregin
    -------------------------------------------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity shiftregINCOMP is
    generic (
    NINPUT : integer := 15
    );
    port (CLK, RST: in std_logic;
    DATAin: in std_logic;
    DATAout: out std_logic_vector (NINPUT-1 downto 0)
    );
    end entity;

    architecture arch of shiftregINCOMP is
    signal tmp : std_logic_vector(NINPUT-1 downto 0);
    begin
    process (CLK, RST)
    begin
    if RST = '0' then
    tmp <= (others => '0');
    elsif CLK'event and CLK = '1' then
    tmp <= tmp(NINPUT-2 downto 0) & DATAin;
    end if;
    end process;
    DATAout <= tmp;
    end arch;

    -------------------------------------------------------------------------------------------------------------------
    -- shiftregout
    -------------------------------------------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity shiftregOUTCOMP is
    generic (
    NOUTPUT : integer := 18
    );
    port (CLK, RST: in std_logic;
    DATAin: in std_logic_vector (NOUTPUT-1 downto 0);
    DATAout: out std_logic;
    ALOAD : in std_logic
    );
    end entity;

    architecture arch of shiftregOUTCOMP is
    signal tmp : std_logic_vector(NOUTPUT-1 downto 0);
    begin
    process (CLK, RST, ALOAD)
    begin
    if RST = '1' then
    tmp <= (others => '0');
    else
    if ALOAD = '1' then
    tmp <= DATAin;
    elsif CLK'event and CLK = '1' then
    tmp <= tmp(NOUTPUT-2 downto 0) & '0';
    end if;
    end if;
    end process;
    DATAout <= tmp(NOUTPUT-1);
    end arch;

    -------------------------------------------------------------------------------------------------------------------

    Synplify gime me a warning telling that the sensitivity list of
    shiftregout is not complete. Is my design correct?
    Thanks a lot!
    gervaz, Feb 16, 2009
    #1
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  2. gervaz

    Tricky Guest

    The warning it's giving is because you assign tmp from DATAin when
    ALOAD = '1', so DATAin also needs to be in the sensitivity list.

    Also, try not to use the ALOAD signal. It will be too prone to meta-
    stability. Try and synchronise it if you can and put it inside the
    clock.

    You have also included packages when you dont need to: std_logic_arith
    and unsigned. They are unnessasry in your design.
    Tricky, Feb 16, 2009
    #2
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