Should VHDL allow Unicode identifiers and comments

[Martin Thompson]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

 

[Christopher Felton]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

b,

Regards,
Chris Fetlon

 

[Mike Treseler]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes

c) Yes, will be helpful in the near future.
Otherwise everyone will have a different library for it.

 

[Martin Thompson]

c) Yes, will be helpful in the near future.
Otherwise everyone will have a different library for it.

I'm not sure I follow Mike - library for what? The original question
was about using Unicode within a VHDL source file (for example, variable
names and comments).

Or are you thinking of having a Unicode "string" replacement - which is
a whole different ballgame, but one we maybe ought to think of also!

Cheers,
Martin

 

[Mike Treseler]

I'm not sure I follow Mike - library for what? The original question
was about using Unicode within a VHDL source file (for example, variable
names and comments).

OK. In that case probably (b) for English speakers.

Or are you thinking of having a Unicode "string" replacement - which is
a whole different ballgame, but one we maybe ought to think of also!

Yes, I was thinking strings.
That seems safe and probably useful.
Programming languages without
Unicode strings built-in suffer as a result.


-- Mike Treseler

 

[Jonathan Bromley]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

I'm not sure I see any use for it. What do you have in mind?

Unicode *strings* and file-IO might well be useful, but
I guess that's a very different story. A new type, either
built-in or in std.standard, for Unicode *characters* would
be a good start.

 

[Martin Thompson]

I'm not sure I see any use for it. What do you have in mind?

The original question was asked without much in mind beyond allowing you
to call a variable 'château' (to pull an example from the other end of
the scale spectrum to our usual fare here

Unicode *strings* and file-IO might well be useful, but
I guess that's a very different story. A new type, either
built-in or in std.standard, for Unicode *characters* would
be a good start.

From other comments, Unicode strings appear to be of much more value
than Unicode identifiers and comments. Although once you allow Unicode
strings in a source file, you've opened the "source-file encoding" can
of worms already, and then (I believe) allowing Unicode in comments
becomes easy. Unicode identifiers may have some negative impact of
parsing efficiency?

In which case, as you say, W_CHARACTER here we (might) come. However,
it also sounds like a large (huge?) amount of work which *may* be better
spent elsewhere.

Cheers,
Martin

 

[Jonathan Bromley]

The original question was asked without much in mind beyond
allowing you to call a variable 'château'

C'est tout possible de faire son logiciel sans aucun accent

it also sounds like a large (huge?) amount of work which
*may* be better spent elsewhere.

I think I tend to agree. The EDA industry as a whole is
irremediably Anglophone, and muddles through pretty well
without internationalization.

 

[Martin Thompson]

The EDA industry as a whole is
irremediably Anglophone,

I like that description

and muddles through pretty well
without internationalization.

and likely will continue to do so!

Thanks,
Martin

 

[Nicholas Collin Paul de Glouceſter]

Martin Thompson <[email protected]> sent on July 28th, 2011:
|-------------------------------------------------------------------------|
|"Hi all, |
| |
|I'm asking for a bit of input from the community... |
| |
|As the title says, would you find it of use to allow Unicode identifiers |
|and comments in a future VHDL revision? |
| |
|Would this be: |
|a) Something VHDL should not allow |
|b) Something that doesn't bother you either way |
|c) Something you'd find useful sometimes |
|d) Something you'd make use of all the time |
|e) Something that you'd switch away from SystemVerilog just to get at |
| (maybe I'm asking the wrong crowd for that |
| |
|Thanks, |
|Martin |
| |
|-- |
|http://parallelpoints.com/ " |
|-------------------------------------------------------------------------|


Hi Mr. Thompson,

I respond more to point out that Unicode support in actual source code
(such as identifiers) was added to Ada and one of the compiler
developers which added this support remarked that it was not worth the
hassle.

Anyhow, as for my own voting: c) or maybe even d). Back to the issue
of hassle in the real World though, there is a valid argument for a)
because many tools such as text editors and terminals are still
screwing up Unicode (such as UTF-8 versus UTF-7) years after it was
introduced. Almost nothing around screws up ASCII (aside from CR and
LF issues).

Regards,
Nicholas Collin Paul de Glouceſter in Unicode (you asked for it)

 

[Anssi Saari]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
c) Something you'd find useful sometimes

I liked an example snippet in Python I saw some time ago. There's
another one at
http://programmers.stackexchange.co...d-to-use-unicode-characters-in-variable-names

for example.

After all, if your angle is phi, then why bother writing it out when
you can just use 'φ' instead?

 

[daniel.kho]

After all, if your angle is phi, then why bother writing it out when

you can just use 'φ' instead?

I like that example. I prefer to write math equations using symbols too, rather than typing in 'English'. Sometimes, greek is better than english whenit comes to math/physics... IMO.

I may not be answering the question, but I will vote:
f) something that the VHDL standard shouldn't be concerned about.

Let the tool vendors concern themselves on this when they have enough customer demand. I believe I won't face much problems when I'm using two different vendor tools (say for synthesis and simulation) who both claim to be Unicode-compliant.

 

[Daniel Leu]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

a) Something VHDL should not allow

Comments would be fine. I am more worried about the entire toolchain: netlist representation, p&r tools, graphical visualization.


- Daniel