Sign extension

Discussion in 'VHDL' started by kclo4, Nov 21, 2006.

  1. kclo4

    kclo4 Guest

    Hi everybody,

    I'd like to know if there is any smart way to extend the sign of
    std_logic_vector

    for exemple :

    data_in : in std_logic_vector(11 downto 0);
    data_out : out std_logic_vector(13 downto 0);

    I want to adjust data_in to data_out size, so what i used to do is:

    data_out <= data_in(11) & data_in(11) & data_in;

    But for huge different size it's painfull and not really nice.
    Is there a smarter way to do it?? May be I should do a function with a
    loop that do it??

    Thank you
     
    kclo4, Nov 21, 2006
    #1
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  2. kclo4 a écrit :
    > Hi everybody,
    >
    > I'd like to know if there is any smart way to extend the sign of
    > std_logic_vector
    >
    > for exemple :
    >
    > data_in : in std_logic_vector(11 downto 0);
    > data_out : out std_logic_vector(13 downto 0);
    >
    > I want to adjust data_in to data_out size, so what i used to do is:
    >
    > data_out <= data_in(11) & data_in(11) & data_in;
    >
    > But for huge different size it's painfull and not really nice.
    > Is there a smarter way to do it?? May be I should do a function with a
    > loop that do it??


    Use ieee.numeric_std package, signed vectors instead of std_logic_vector
    and resize function.

    data_out <= resize(data_in, data_out'length);

    Nicolas
     
    Nicolas Matringe, Nov 21, 2006
    #2
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  3. kclo4

    OL Guest

    kclo4 a écrit :
    > Hi everybody,
    >
    > I'd like to know if there is any smart way to extend the sign of
    > std_logic_vector
    >
    > for exemple :
    >
    > data_in : in std_logic_vector(11 downto 0);
    > data_out : out std_logic_vector(13 downto 0);
    >
    > I want to adjust data_in to data_out size, so what i used to do is:
    >
    > data_out <= data_in(11) & data_in(11) & data_in;
    >
    > But for huge different size it's painfull and not really nice.
    > Is there a smarter way to do it?? May be I should do a function with a
    > loop that do it??
    >
    > Thank you


    You have it for free in the std_logic_arith package:
    function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;

    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_SIGNED.ALL;
    [...]
    data_out <= SXT(data_in, data_out'LENGTH);

    You also have the EXT function, which is the simple extension function
    _without_ sign extension.
     
    OL, Nov 21, 2006
    #3
  4. kclo4

    Andy Guest

    Many users don't recommend using non-ieee packages such as
    std_logic_arith, etc. that were developed by synopsys and compiled into
    the ieee library without ieee permission/standardization. Since they
    are not standard, their implementation can and does vary between
    vendors of simulation and synthesis tools.

    Better to type a little more and use ieee standard packages that are
    uniform in their implementation across all vendors. If you need to keep
    data_in and data_out as SLV:

    data_out <= std_logic_vector(resize(signed(data_in), data_out'length));

    Andy


    OL wrote:
    > kclo4 a écrit :
    > > Hi everybody,
    > >
    > > I'd like to know if there is any smart way to extend the sign of
    > > std_logic_vector
    > >
    > > for exemple :
    > >
    > > data_in : in std_logic_vector(11 downto 0);
    > > data_out : out std_logic_vector(13 downto 0);
    > >
    > > I want to adjust data_in to data_out size, so what i used to do is:
    > >
    > > data_out <= data_in(11) & data_in(11) & data_in;
    > >
    > > But for huge different size it's painfull and not really nice.
    > > Is there a smarter way to do it?? May be I should do a function with a
    > > loop that do it??
    > >
    > > Thank you

    >
    > You have it for free in the std_logic_arith package:
    > function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
    >
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_SIGNED.ALL;
    > [...]
    > data_out <= SXT(data_in, data_out'LENGTH);
    >
    > You also have the EXT function, which is the simple extension function
    > _without_ sign extension.
     
    Andy, Nov 21, 2006
    #4
  5. kclo4

    Andy Guest

    Or if you use appropriately constrained subtypes of integer for
    data_out and data_in:

    data_out <= data_in;

    Andy


    Nicolas Matringe wrote:
    > kclo4 a écrit :
    > > Hi everybody,
    > >
    > > I'd like to know if there is any smart way to extend the sign of
    > > std_logic_vector
    > >
    > > for exemple :
    > >
    > > data_in : in std_logic_vector(11 downto 0);
    > > data_out : out std_logic_vector(13 downto 0);
    > >
    > > I want to adjust data_in to data_out size, so what i used to do is:
    > >
    > > data_out <= data_in(11) & data_in(11) & data_in;
    > >
    > > But for huge different size it's painfull and not really nice.
    > > Is there a smarter way to do it?? May be I should do a function with a
    > > loop that do it??

    >
    > Use ieee.numeric_std package, signed vectors instead of std_logic_vector
    > and resize function.
    >
    > data_out <= resize(data_in, data_out'length);
    >
    > Nicolas
     
    Andy, Nov 21, 2006
    #5
  6. Nicolas Matringe schrieb:


    > Use ieee.numeric_std package, signed vectors instead of std_logic_vector
    > and resize function.
    >
    > data_out <= resize(data_in, data_out'length);


    Respectively with std_ulogic_vector and the desired conversions:

    -- either
    data_out<=std_ulogic_vector(resize(unsigned(data_in), data_out'length));
    -- or
    data_out<=std_ulogic_vector(resize( signed(data_in), data_out'length));

    (I only want to point it out that sign extension of std_ulogic_vectors
    strongly depends on the fact whether signed or unsigned data
    representation is desired.)

    Ralf
     
    Ralf Hildebrandt, Nov 21, 2006
    #6
  7. kclo4

    Andy Guest

    There is no "sign extension" of unsigned representations, since there
    is no sign bit. A resize of an unsigned representation to a larger size
    just appends enough zeroes to fit, whereas sign extension replicates
    the MSB enough times to fit.

    The numeric_std.resize() function is overloaded to perform a sign
    extend operation when called with a signed argument and return value
    (assuming it is increasing the size of the argument).

    Andy


    Ralf Hildebrandt wrote:
    > Nicolas Matringe schrieb:
    >
    >
    > > Use ieee.numeric_std package, signed vectors instead of std_logic_vector
    > > and resize function.
    > >
    > > data_out <= resize(data_in, data_out'length);

    >
    > Respectively with std_ulogic_vector and the desired conversions:
    >
    > -- either
    > data_out<=std_ulogic_vector(resize(unsigned(data_in), data_out'length));
    > -- or
    > data_out<=std_ulogic_vector(resize( signed(data_in), data_out'length));
    >
    > (I only want to point it out that sign extension of std_ulogic_vectors
    > strongly depends on the fact whether signed or unsigned data
    > representation is desired.)
    >
    > Ralf
     
    Andy, Nov 21, 2006
    #7
  8. Andy schrieb:

    > There is no "sign extension" of unsigned representations, since there
    > is no sign bit. A resize of an unsigned representation to a larger size
    > just appends enough zeroes to fit, whereas sign extension replicates
    > the MSB enough times to fit.


    Yes, I know - but I wanted to point out, that nobody can say, what is
    inside a std_logic_vector: just bits, signed or unsigned data.
    And even adding zeros while resizing an unsigned vector is some kind of
    sign extension, because an unsigned vector has always an implicit zero
    as sign.

    Ralf
     
    Ralf Hildebrandt, Nov 22, 2006
    #8
  9. kclo4 wrote:
    > Hi everybody,
    >
    > I'd like to know if there is any smart way to extend the sign of
    > std_logic_vector
    >
    > for exemple :
    >
    > data_in : in std_logic_vector(11 downto 0);
    > data_out : out std_logic_vector(13 downto 0);
    >
    > I want to adjust data_in to data_out size, so what i used to do is:
    >
    > data_out <= data_in(11) & data_in(11) & data_in;
    >
    > But for huge different size it's painfull and not really nice.
    > Is there a smarter way to do it?? May be I should do a function with a
    > loop that do it??
    >
    > Thank you



    Don't need any libraries or loops if you do this:

    data_out(11 downto 0) <= data_in;
    data_out(13 downto 12) <= (13 downto 12 => data_in(11));
     
    Magne Munkejord, Nov 22, 2006
    #9
  10. Ralf Hildebrandt a écrit :

    > (I only want to point it out that sign extension of std_ulogic_vectors
    > strongly depends on the fact whether signed or unsigned data
    > representation is desired.)


    I assumed that sign extension was only needed for signed vectors.

    Nicolas
     
    Nicolas Matringe, Nov 22, 2006
    #10
  11. kclo4

    Alexis GABIN Guest

    Thanks you all for your usefull answers,


    > Don't need any libraries or loops if you do this:
    >
    > data_out(11 downto 0) <= data_in;
    > data_out(13 downto 12) <= (13 downto 12 => data_in(11));


    I like this way but shouldn't it be? :
    data_out(13 downto 12) <= (others => data_in(11));

    Probably both work?, I will try myself to check

    Thanks

    alexis
     
    Alexis GABIN, Nov 23, 2006
    #11
  12. kclo4

    sabgg

    Joined:
    May 18, 2011
    Messages:
    1
    Hi ;

    how can I use this function (SXT) for an arithmetic fonction for exemple I want to do something like that : y<= (x+w)*z ;

    I tried to use it in a code but I am on the wrong way can you help me please

    thanks .


    "sorry for my english"
     
    sabgg, May 18, 2011
    #12
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