Signal assignment inside for loop

Discussion in 'VHDL' started by krkrkr, Jun 14, 2009.

  1. krkrkr

    krkrkr

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    Hello all,
    I'm new to VHDL and having a problem.

    I know that signal assignment does not take effect until the end of the process unlike the variable assignment.
    ie cnt <= cnt +1;
    out <= cnt;
    If cnt is a signal then out will have the value of cnt before adding 1.

    My problem is I want to have same kind of signal assignment inside a for loop
    ie for i 0 to 2 loop
    cnt <= cnt +1;
    end loop;

    cnt is a signal, how can i do that and have the right cnt value?

    Thanks.
     
    krkrkr, Jun 14, 2009
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  2. krkrkr

    debayan_p

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    for i 0 to 2 loop
    cnt <= cnt +1;
    end loop;

    The above is ok if you declare 'cnt' as a variable. Is it necessary to declare it as a signal ?

    Later when ur looping is complete you can saaign the variable 'cnt' to a signal or an output port.
     
    debayan_p, Jun 17, 2009
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