Signal Conditional Assignment ?

Discussion in 'VHDL' started by guylewis, Nov 15, 2008.

  1. guylewis

    guylewis

    Joined:
    Nov 14, 2008
    Messages:
    3
    Can anyone help with explaining how the statement below works? I'm confused as to why you AND data_out?

    Statement in question
    -------------------------
    read_mux_out <= A_REP(to_std_logic((((std_logic_vector'("000000000 000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 13) AND data_out;

    Thanks for any help
    Guy
     
    guylewis, Nov 15, 2008
    #1
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