Signal driven inside versus outside the process

Discussion in 'VHDL' started by jka_singh, May 10, 2011.

  1. jka_singh

    jka_singh

    Joined:
    May 10, 2011
    Messages:
    1
    Hello All,

    I have a 'general interest' question about the following code..
    This is not my code and I am trying to understand it, without running a sim.

    P2S_Output: PROCESS (CLK,reset,FRAME)
    BEGIN
    IF (reset = '0' OR reset = 'L') THEN
    Serial_Out <= (others => '0');
    elsIF (CLK'EVENT AND CLK = '0') THEN
    if (FRAME='1') then
    Serial_Out <= p_in;
    else
    Serial_Out <= "0" & Serial_Out(63 downto 1);
    end if;
    end if;
    DOUT <= Serial_Out(0);
    END PROCESS P2S_Output;


    1) Is it true that at the end of the process (delta time) DOUT would have 'old/previous' value of 'Serial_Out' ? I am saying this, as new value to Serial_Out will not be assigned, till the process ends.

    2) Is this a 'good' way to code? Or is there a better to assign old value of Serial_Out to DOUT?

    Thanks
    jka_singh, May 10, 2011
    #1
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  2. jka_singh

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    I think it's fine (though one might say it may be "nicer" to use a variable to make it more explicit the old value is copied rather than the new one)

    BTW it is unnecessary FRAME is listed in the sensitivity list. This may cause a little bit of extra (unnecessary) checking the signal by a simulator (it is not incorrect, but it may take some time doing those checks)
    joris, May 12, 2011
    #2
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