signal is never used warning

Discussion in 'VHDL' started by mosh11, May 29, 2008.

  1. mosh11

    mosh11

    Joined:
    May 29, 2008
    Messages:
    2
    hello

    there is a warning in my vhdl code when i try to synthesize it.the warning says that input clk and input start1 is never used.
    the code should be burned to a Fpga to drive 4 motors to control a robotic arm
    the code is based on the clk which will be the fpga clock.
    so if input clk is never used the code will not function.
    when i burned it to the fpga the code didn't do its function.

    here is the code

    Code:
    ----------------------------------------------------------------------------------
    -- Company: 
    -- Engineer: 
    -- 
    -- Create Date:    08:25:51 05/25/2008 
    -- Design Name: 
    -- Module Name:    tarek - Behavioral 
    -- Project Name: 
    -- Target Devices: 
    -- Tool versions: 
    -- Description: 
    --
    -- Dependencies: 
    --
    -- Revision: 
    -- Revision 0.01 - File Created
    -- Additional Comments: 
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    
    entity tarek is
        Port ( reset : inout  STD_LOGIC;
               start1 : in  STD_LOGIC;
               clk :    in std_logic;
               m1_0 : out  STD_LOgic;
               m1_1 : out  STD_LOGIC;
               m2_0 : out  STD_LOgic;
               m2_1 : out  STD_LOGIC;
               m3_0 : out std_logic;
               m3_1 : out  STD_LOGIC;
               m4_0 : out  STD_LOGIC;
               m4_1 : out std_logic
    			  );
    end tarek;
    
    architecture Behavioral of tarek is
    
     signal count,qnt : integer;
    
    begin
    
     process(clk,reset)
     begin
      if (reset='1' )then
      m1_0<='0';m1_1<='0';
      m2_0<='0';m2_1<='0';
      m3_0<='0';m3_1<='0';
      m4_0<='0';m4_1<='0';
     else
     if(start1='1')
       then   if (rising_edge(clk))
    	   then if count+1>(29/10)*10**9
    		then qnt<=qnt+1;
          else
    		 count<=count+1;
          end if;
    		end if;
     if(count>0 and (count-1)<10**9) -- wait for 20s
     then
         m1_0<='0';m1_1<='1';
    	  m2_0<='0';m2_1<='0';
    	  m3_0<='0';m3_1<='0';
    	  m4_0<='0';m4_1<='0'; --m1_0;m1_1 : right & left motor
     
     elsif (count>10**9 and (count-1)<(3/2)*10**9) -- wait for 10s 
     then
         m2_0<='0';m2_1<='1';
         m1_0<='0';m1_1<='0';
         m3_0<='0';m3_1<='0';
    	  m4_0<='0';m4_1<='0';	  -- m2_0;m2_1 : forward & back motor
    
     elsif (count>(3/2)*10**9 and (count-1)<2*10**9) -- wait for 10s
     then
         m1_0<='0';m1_1<='0';
    	  m2_0<='0';m2_1<='0';
    	  m4_0<='0';m4_1<='0';
    	  m3_0<='1';m3_1<='0';     -- m3_0;m3_1 : up & down motor
    
     elsif (count>2*10**9 and count-1<(9/4)*10**9)  -- wait for 5s 
     then
         m1_0<='0';m1_1<='0';
    	  m2_0<='0';m2_1<='0';
    	  m3_0<='0';m3_1<='0';
         m4_1<='1';m4_0<='0'; -- m4_0;m4_1 : holding motor
     elsif (count>(9/4)*10**9 and count-1<(12/5)*10**9)
        then  
    	  m1_0<='0';m1_1<='0';
    	  m2_0<='0';m2_1<='0';
    	  m3_0<='0';m3_1<='0';
         m4_0<='1';m4_1<='0'; 
     elsif(count>(12/5)*10**9 and count-1<(29/10)*10**9)
     then
    
         m1_0<='0';m1_1<='0';
    	  m2_0<='0';m2_1<='0';
    	  m4_0<='0';m4_1<='0'; 
         m3_0<='0';m3_1<='1';
     elsif(qnt>0 and qnt-1<(1/2)*10**9)
     then 
     
         m1_0<='0';m1_1<='0';
    	  m3_0<='0';m3_1<='0';
    	  m4_0<='0';m4_1<='0';
         m2_0<='1';m2_1<='0';
     elsif(qnt>(1/2)*10**9 and qnt-1<(3/2)*10**9)
     then
    
    	  m2_0<='0';m2_1<='0';
    	  m3_0<='0';m3_1<='0';
    	  m4_0<='0';m4_1<='0'; 
         m1_0<='1';m1_1<='0';
     elsif (qnt>(3/2)*10**9 and qnt-1<2*10**9)
     then
     
         m1_0<='0';m1_1<='0';
    	  m2_0<='0';m2_1<='0';
    	  m4_0<='0';m4_1<='0';
         m3_0<='1';m3_1<='0';
     
     elsif(qnt>2*10**9 and qnt-1<(9/4)*10**9)
     then
     
         m1_0<='0';m1_1<='0';
    	  m2_0<='0';m2_1<='0';
    	  m3_0<='0';m3_1<='0';
         m4_0<='1';m4_1<='0';	  
     elsif(qnt>(9/4)*10**9)
     then
         reset<='1';
     end if;
     end if;
     end if; 
     end process;
    
    end Behavioral;
    
    
    
     
    mosh11, May 29, 2008
    #1
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  2. mosh11

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    1) I don't "like" the way you controls Reset inside the process.
    Coulden't put the Start1='1' test inside the Rising_edge(clk) block.

    not much but may be enough
    Jeppe
     
    jeppe, May 31, 2008
    #2
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