Signal is not constrained

Discussion in 'VHDL' started by sasa, Oct 15, 2008.

  1. sasa

    sasa

    Joined:
    Oct 12, 2008
    Messages:
    2
    Hi, I have the following problem when i writing my testbench. it poped up the following error when i run my testbench.

    Signal operator is not constrained.

    Anyone knows what the problem is?

    Thanks.
     
    sasa, Oct 15, 2008
    #1
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