signal update problem

Discussion in 'VHDL' started by sohannin, Jan 28, 2006.

  1. sohannin

    sohannin Guest

    I have a small part in my code like this (this is completely bogus but the
    idea is the same):

    process (ck)
    ....
    internal_sum_2(0) <= internal_sum(0) XOR my_signal(0);
    internal_sum_2(7 downto 1) <= internal_sum(7 downto 1) XOR "0000001";

    sum <= internal_sum_2;
    end process;
    ....

    So this process is synchronous and signals update the sum which is
    out-port. But why do they update the sum at both instances, i.e. the first
    clause updating only the lowest bit of internal_sum_2 causes a change in
    the output port "sum" immediately even though statements inside the
    process should be sequential? My intention is to first construct the whole
    8-bit vector and update the output port's all bits at the same time. What
    am I doing wrong?
    sohannin, Jan 28, 2006
    #1
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  2. sohannin

    kameshwar_kaushik

    Joined:
    Jan 26, 2006
    Messages:
    6
    try using a variable inside the process block to do ur operations and then assign it back to out-port at the end of process block .... i think, use of a variable rather than a signal will solve ur problem
    kameshwar_kaushik, Jan 29, 2006
    #2
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  3. sohannin

    amitesh Guest

    you should put sum in a separate process with internal_sum_2(7) in the
    sensitivity list.
    sohannin wrote:
    > I have a small part in my code like this (this is completely bogus but the
    > idea is the same):
    >
    > process (ck)
    > ...
    > internal_sum_2(0) <= internal_sum(0) XOR my_signal(0);
    > internal_sum_2(7 downto 1) <= internal_sum(7 downto 1) XOR "0000001";
    >
    > sum <= internal_sum_2;
    > end process;
    > ...
    >
    > So this process is synchronous and signals update the sum which is
    > out-port. But why do they update the sum at both instances, i.e. the first
    > clause updating only the lowest bit of internal_sum_2 causes a change in
    > the output port "sum" immediately even though statements inside the
    > process should be sequential? My intention is to first construct the whole
    > 8-bit vector and update the output port's all bits at the same time. What
    > am I doing wrong?
    amitesh, Jan 30, 2006
    #3
  4. sohannin

    anupam Guest

    Are you sure about the code written here is the same as code you are
    running?
    Because this happens when the internal_sum or the sum is a variable
    .......
    Shouldn't happen in this case ....
    The signals are updated sequentially after a delta delay in a
    process....

    regards,
    Anupam Jain
    anupam, Jan 31, 2006
    #4
  5. sohannin

    sohannin Guest

    On Tue, 31 Jan 2006 05:57:17 +0200, anupam <> wrote:

    Yes, quite sure. ;)

    Internal sum wasn't a variable, but now it is. And now it works, for some
    reason. I had to change all the internal signals to variables to cause the
    sum to update only when the result is ready.

    > Are you sure about the code written here is the same as code you are
    > running?
    > Because this happens when the internal_sum or the sum is a variable
    > ......
    > Shouldn't happen in this case ....
    > The signals are updated sequentially after a delta delay in a
    > process....
    sohannin, Jan 31, 2006
    #5
  6. sohannin

    sohannin Guest

    On Mon, 30 Jan 2006 11:29:46 +0200, amitesh <> wrote:

    > you should put sum in a separate process with internal_sum_2(7) in the
    > sensitivity list.


    Hmm, that's a good idea, thanks! Although it now works with variables.
    sohannin, Jan 31, 2006
    #6
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