Signal use from pin

Discussion in 'VHDL' started by ALuPin, Apr 28, 2005.

  1. ALuPin

    ALuPin Guest

    Hi newsgroup,

    in my last post "SYNC + FIFO" I talked about the sychronization method
    of an external data stream.
    Additional to the bus data I have some control signals coming from
    the USB transceiver which are also synchronous to the RXCLK which
    I use as the FIFO write clock (see last post).

    In order to respond directly to the control signals I get from the
    transceiver(for example:
    USB transceiver drives one control signal high to notify the FPGA to
    place the next data byte on the DATA[7..0] bus)
    I have to use the control signal from the pin in my state machine
    running
    with the RXCLK.

    What recommendations do you make when using such a signal from a pin
    with regard to placement, timing constraints etc. ?

    Thank you for your great help.

    Rgds
    André
    ALuPin, Apr 28, 2005
    #1
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  2. ALuPin

    Gabor Guest

    ALuPin wrote:
    > Hi newsgroup,
    >
    > in my last post "SYNC + FIFO" I talked about the sychronization

    method
    > of an external data stream.
    > Additional to the bus data I have some control signals coming from
    > the USB transceiver which are also synchronous to the RXCLK which
    > I use as the FIFO write clock (see last post).
    >
    > In order to respond directly to the control signals I get from the
    > transceiver(for example:
    > USB transceiver drives one control signal high to notify the FPGA to
    > place the next data byte on the DATA[7..0] bus)
    > I have to use the control signal from the pin in my state machine
    > running
    > with the RXCLK.
    >
    > What recommendations do you make when using such a signal from a pin
    > with regard to placement, timing constraints etc. ?
    >
    > Thank you for your great help.
    >
    > Rgds
    > André



    If latency is not an issue, I would register the control signal at the
    IOB to make sure you don't have setup timing issues. Then add another
    delay stage (register) for the DATA[7..0] bus so you can use the
    control signal a cycle later.

    If you need to reduce latency into your FIFO, you need to create a
    timing spec in the ucf file for the control signal like:
    OFFSET = IN 7.2 ns BEFORE "RXCLK";
    to make sure your state machine does not exceed the input setup
    time available.

    If you haven't assigned pins yet, I would suggest grouping the control
    pin near the data pins so your state machine can be placed easily
    near the control input.
    Gabor, Apr 28, 2005
    #2
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  3. ALuPin

    Guest

    > If latency is not an issue, I would register the control signal at
    the
    > IOB to make sure you don't have setup timing issues. Then add

    another
    > delay stage (register) for the DATA[7..0] bus so you can use the
    > control signal a cycle later.
    >
    > If you need to reduce latency into your FIFO, you need to create a
    > timing spec in the ucf file for the control signal like:
    > OFFSET = IN 7.2 ns BEFORE "RXCLK";
    > to make sure your state machine does not exceed the input setup
    > time available.
    >
    > If you haven't assigned pins yet, I would suggest grouping the

    control
    > pin near the data pins so your state machine can be placed easily
    > near the control input.



    How can I make this timing constraint "OFFSET X BEFORE Clk" in
    QuartusII ?

    Thank you for your help.

    Rgds
    Andre
    , May 4, 2005
    #3
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